參數(shù)資料
型號(hào): MT90500
廠商: Mitel Networks Corporation
英文描述: Multi-Channel ATM AAL1 SAR
中文描述: 多通道自動(dòng)柜員機(jī)AAL1特區(qū)
文件頁數(shù): 12/159頁
文件大小: 514K
代理商: MT90500
MT90500
12
1.2
Reference Documents
MT90500 Programmer’s Manual.
MSAN-171 - TDM Clock Recovery from CBR-over-ATM Links Using the MT90500.
ITU-T Rec. I.363.1, “B-ISDN ATM Adaptation Layer Specification: Type 1 AAL,” 08/1996.
ANSI T1.630, “Broadband ISDN - ATM Adaptation Layer for Constant Bit Rate Services Functionality and
Specification,” 1993.
AF-PHY-0017, “UTOPIA, An ATM-PHY Interface Specification: Level 1, Version 2.01,” March 21, 1994.
AF-VTOA-0078.000, “Circuit Emulation Service Interoperability Specification, Version 2.0,” Jan. 1997.
AF-VTOA-0083.000, “Voice and Telephony Over ATM to the Desktop Specification, Version 2.0,” May 1997.
M. Noorchasm et al., “Buffer Design for Constant Bit Rate Services in Presence of Cell Delay Variation,” ATM
Forum Contribution 95-1454.
Paul E. Fleischer and Chi-Leung Lau, “Synchronous Residual Time Stamp for Timing Recovery in a Broadband
Network,” United States Patent 5,260,978, Nov. 1993.
IEEE Std. 1149.1a-1993, “IEEE Standard Test Access Port and Boundary Scan Architecture.”
Figure 1 - MT90500 Block Diagram
TDM Bus
Interface
Logic
TX
AAL1
SAR
RX
AAL1
SAR
TDM Bus
16 lines
2048 x 64kbps
(max.)
TX UTOPIA
MUX
RX
UTOPIA
BLOCK
VC Look-up
Tables
TX / RX Control
Structures and
Circular Buffers
Main
UTOPIA
Interface
Secondary
UTOPIA
Interface
Boundary-
Scan Logic
From
External
SAR
To/From
External
PHY
JTAG Interface
16-bit Microprocessor Inter-
face
External Memory
Controller
TDM Clock
Logic
Clock
Signals
External
Synchronous
SRAM
TDM Module
Internal
TDM
Frame
Buffer
Microprocessor
Interface Logic
Registers
UTOPIA Module
Local TDM Bus
32 x 64 kbps in /
32 x 64 kbps out
Clock
Recovery
MT90500
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