參數(shù)資料
型號： MT90500
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR
中文描述： 多通道自動柜員機(jī)AAL1特區(qū)
文件頁數(shù)： 98/159頁
文件大小： 514K
代理商： MT90500
MT90500
98
5.2.5
TDM Interface and Clock Interface Registers
Table 47 - TDM Interface Control Register
Address: 6000 (Hex)
Label: TDMCNT
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
TIENA
0
R/W
TDM to/from Internal Memory Process Enable. ‘0’=Disabled; ‘1’=Enabled.
IEENA
1
R/W
Internal to/from External Memory Process Enable. ‘0’=Disabled; ‘1’=Enabled.
GENOE
2
R/W
General Output Enable. Enables TDM data outputs and inputs.
‘0’ = TDM data output pins tristated and TDM output (i.e. receive) data is looped back as
TDM input (i.e. transmit) data;
‘1’ = Normal TDM operation.
In order to prevent collisions on the TDM bus, one should clear all of the Output Enable
Registers (addresses 7000 + 2N) prior to setting this bit.
When LOW, disables CFAIL and CABS bits in the TDM Interface Status Register (6002h).
CLK_LOOPBACK
3
R/W
TDM Clock Loopback.
‘0’ = Normal operation;
‘1’ = Loopback.
In loopback the CLKx2, CLKx1, and FSYNC input signals are replaced by the internally
generated clocks, but the clock pins are not driven by the MT90500.
CABSIE
4
R/W
Clock Absent Interrupt Enable. ‘0’=Disabled; ‘1’=Enabled. When enabled, a ‘1’ on CABS in
Register 6002h will force a ‘1’ on TDM_SERV in Register 0002h.
CFAILIE
5
R/W
Clock Fail Interrupt Enable. ‘0’=Disabled; ‘1’=Enabled. When enabled, a ‘1’ on CFAIL in
Register 6002h will force a ‘1’ on TDM_SERV in Register 0002h.
TOBIE
6
R/W
TDM Out of Bandwidth Interrupt Enable. ‘0’=Disabled; ‘1’=Enabled. When enabled, a ‘1’ on
TOB in Register 6002h will force a ‘1’ on TDM_SERV in Register 0002h.
TRUEIE
7
R/W
TDM Read Underrun Error Interrupt Enable. ‘0’=Disabled; ‘1’=Enabled. When enabled, a
‘1’ on TRUE in Register 6002h will force a ‘1’ on TDM_SERV in Register 0002h.
TRUCRIE
8
R/W
TDM Read Underrun Counter Rollover Interrupt Enable. ‘0’=Disabled; ‘1’=Enabled. When
enabled, a ‘1’ on TRUCR in Register 6002h will force a ‘1’ on TDM_SERV in Register
0002h.
Reserved
14:9
R/O
Reserved. Always read as “000_000”.
TESTS
15
R/W
TEST Status. Forces all status events in both the TDM Interface Status Register (6002h)
and the Clock Module General Status Register (6082h) to occur. Also causes the TDM
Read Underrun Count Register (6048h) to be incremented and the TDM Read Underrun
Address Register (6046h) to be updated. Used for test purposes only.
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
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MT90502_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
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