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參數(shù)資料
| 型號： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動柜員機(jī)AAL1特區(qū) |
| 文件頁數(shù)： | 70/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
70
4.6
Clock Recovery from ATM Link
4.6.1
Adaptive Clock Recovery Sub-Module
Adaptive Clock Recovery is a flexible method for TDM clock recovery from an ATM link. There are several
approaches to adaptive clock recovery, and the standards do not require a specific one, so adaptive clock
recovery is termed “non-standardized.” The implementation given here is similar to the general outline in ITU-T
I.363.1. In the MT90500, adaptive clock recovery uses a reference 8 kHz clock to generate the TDM clock
signals. The TDM clocks are controlled by adjusting the reference 8 kHz clock frequency according to the
arrival rate of ATM cells on a designated VC.
As seen in Figure 31, the reception rate of timing reference cells or 8 kHz markers (EX_8KA) is used as the
basis for the adaptive clock recovery scheme implemented by this sub-module. This block is responsible for
generating (under software control) a reference clock signal (RXVCLK) based on the rate of reception of the
timing reference cells or markers. The sub-module additionally implements a state machine (seen in Figure 32)
which tracks the cell arrival rate, checks the cell sequence numbers for lost or misinserted cells or cells with
bad SNP fields (to a maximum of one), and adjusts for discrepancies.
The Adaptive Clock Recovery Block consists of:
a Timing Reference Cell Processing unit which generates an event (“new_cell”) every time a timing
reference cell is received. A timing reference cell is defined as an AAL1 cell whose VPI/VCI matches
that specified in the VPI Timing Register (401Ah) and the VCI Timing Register (401Ch). OAM cells on
the specified VPI/VCI are ignored, as they do not carry CBR data. The unit can compensate for a single
lost or misinserted cell or bad sequence number protection (SNP). It will also flag an out-of-sync error
when more than one cell is lost, misinserted, or received with corrupted sequence number protection.
SNP-checking is enabled by setting the Seq_CRC_Ena bit in the Timing Reference Processing Control
Register at 60A0h. If no timing reference cell is received within a certain period (user-definable by
setting bits<9:0> in the same register), it will generate a loss of timing reference cell error. The state
machine for this unit is shown in Figure 32:
DIV 8
Counter
new_cell
EX_8KA
CLKx1
EX_8KA
0
1
DIVX Register (60A8h)
DIVX Ratio Register (60AAh)
RXVCLK
Cell / 8 kHz
MCLK
Timing Reference
Cell Processing
Event Counter
Temp Register
CLKx1 Count
Registers (60A4h
and 60A6h)
Event Count
Register (60A2h)
External PLL
CNTUPDATE
REFSEL<1:0> = 01
REF8KCLK
CLKx1
CLKx2
8 kHz
designated
timing VC
Figure 31 - Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram)
MT90500
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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