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參數(shù)資料
| 型號： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動柜員機AAL1特區(qū) |
| 文件頁數(shù)： | 55/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
55
4.3.3
Non-CBR Data Cell Transmission Capability
The TX_SAR also has the ability to transmit CPU-written non-CBR data cells directly from a user-defined FIFO
in external memory (the Transmit Data Cell FIFO) to the UTOPIA module. Non-CBR data cells include OAM
cells, other signalling cells, and AAL5 cells containing CPU data. Once the CPU writes the complete cell into
the Transmit Data Cell FIFO, the UTOPIA module then treats these non-CBR data cells the same as the normal
CBR cells. All 53 bytes of the non-CBR data cells are written by the microprocessor into the FIFO in 64-byte
long structures located on 64-byte boundaries (see Figure 21). There are 16, 32, 64 or 128 of these structures
contained in the circular FIFO, mapped in the external memory at the address determined by the Transmit Data
Cell FIFO Base Address Register (register 2050h). This FIFO must not overlap an 8-Kbyte boundary. If the
FIFO does overlap an 8K boundary, some or all of the non-CBR cells sent by the TX_SAR will be corrupted.
There are two ways to control transmission of non-CBR data cells: by scheduler, or by AUTODATA. The
scheduler method requires mapping data cell events into one of the transmission schedulers being used. This
is done by writing “001” in the Entry Type section of the VC Pointer entry, as shown in Figure 20.
In this case, when the scheduler hits the frame within which this entry is contained, it will read the next valid
data cell from the Transmit Data Cell FIFO and transmit it. Because non-CBR cell transmission does not
require the use of Transmit Control Structures, the TX_Struct_Pnt field in the VC Pointer is not used and thus
its value is irrelevant. Note that using the scheduler(s) to control non-CBR data transmission results in regularly
spaced non-CBR data cells, as specified in the scheduler entries.
The other possibility for controlling transmission of non-CBR data cells is by using the AUTODATA bit in the
TX_SAR Control Register at 2000h. While that bit is HIGH, once the TX_SAR has completed its assigned cells
for a certain quad frame (or frame) and is waiting for its next pulse (i.e. the TX_SAR is idle), the MT90500 will
automatically transmit data cells, provided that data cells are available in the Transmit Data Cell FIFO. This
process will end as soon as the next pulse is detected (
Note:
The non-CBR cell being treated at that time will
be completed before the TX_SAR returns to CBR cell assembly).
Both these cases require the microprocessor to write the full non-CBR data cell into the Transmit Data Cell
FIFO, and then to write the new (incremented) value of the Transmit Data Cell FIFO Write Pointer (address
2052h). Non-CBR data cells will only be sent if the Transmit Data Cell FIFO Write Pointer and the Transmit
Data Cell FIFO Read Pointer (address 2054h) indicate that there are valid cells contained in the FIFO. When
the pointers are not equal, the TX_SAR goes to the appropriate address indicated by the Transmit Data Cell
FIFO Base Address Register (address 2050h) and reads the non-CBR data cell. Note that although the FIFO
read pointer will be automatically adjusted to fit the Transmit Data Cell FIFO size (for example, if the FIFO size
is 32 cells, when the read pointer is 31 and a cell is read, it will wrap around to 0), that is not true of the write
pointer. Therefore, if the FIFO write pointer is set to 128, non-CBR cells will always be considered valid.
0
2
3
4
15
0
XXXX XXXX XXXX
001
VC Pointer
2
3
4
15
R
TX_Struct_Pnt
T
R = Reserved (must be set to ‘0’)
T = Entry Type (000 = inactive; 001 = non-CBR
data; 010 = AAL1/CBR-AAL0; 111 = CBR-AAL5;
all others: Reserved)
0
Figure 20 - VC Pointer For Scheduler-Controlled Non-CBR Data Cell
相關PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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