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參數(shù)資料
| 型號： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁數(shù)： | 99/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
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MT90500
99
Table 48 - TDM Interface Status Register
Address: 6002 (Hex)
Label: TIS
Reset Value: XX00
Label
Bit
Position
Type
Description
Reserved
3:0
R/O
Reserved. Always read as “0000”.
CABS
4
R/O/L
Clock Absent. This flag is raised when one or more of the three TDM clock pins (CLKX2,
CLKX1, and FSYNC) has not changed state within a specified number of MCLK cycles.
The signals are monitored when the pins are inputs (TDM Clock Slave or Clock Master
Alternate modes), and also when the pins are outputs (TDM Clock Master mode).
This flag is disabled when GENOE is LOW. Writing a ‘1’ over this bit clears it.
Note when TCLKSYN in register 6010h is set to ‘1’ in TDM Slave mode, the CLKx1 pin is
not used as an output but remains high-impedance. The CABS bit will therefore report a
loss of clocks unless an external signal is present at the CLKx1 pin.
CFAIL
5
R/O/L
SCSA Clock Fail. This flag is used only when the MT90500 is NOT the clock master (i.e.
configured as Slave or as Clock Master Alternate in SCSA mode). This flag is raised and
latched when the CLKFAIL pin is sampled HIGH and the CORSIGA pin is configured as
CLKFAIL input (i.e. CORSIGACNF in 6004h must be “11”). The CORSIGA bit in this
register can be used to verify the current state of the CLKFAIL signal.
When this bit is HIGH, and the CLK_ALT bit in 6010h is HIGH, the MT90500 will drive
the TDM clock lines (switch from Master Alternate to Master) and if CORSIGACNF is
“11”, drive 0 out on CORSIGA/CLKFAIL.
This flag is disabled when GENOE is LOW. Writing a ‘1’ over this bit clears it.
TOB
6
R/O/L
TDM Out of Bandwidth. This flag is raised when the internal to/from external memory
process is unable to transfer all the data in the specified time. This flag generally
indicates that there is a bandwidth limitation in accesses to external memory. External
memory access requirements must be reduced, or external memory speed must be
increased. The IEENA bit in the TDM Interface Control Register at 6000h must be set for
this error to be generated.
Writing a ‘1’ over this bit clears it.
TRUE
7
R/O/L
TDM Read Underrun Error. ‘0’ = Error has not occurred. ‘1’ = An underrun has occurred.
Indicates the occurrence of an underrun on a TDM read from one of the Receive Circular
Buffers. This error-indication is controlled by the TDM Read Underrun Detection Enable
(U) bits in the External Memory to Internal TDM Memory Control Structure (i.e. if the U
bits are LOW, no underrun errors will be noted in this register).
Writing a ‘1’ over this bit clears it.
TRUCR
8
R/O/L
TDM Read Underrun Count Rollover. This flag is raised when the underrun counter at
register 6048h returns to 0000h. Writing a ‘1’ over this bit clears it.
TDMSERV
9
R/O
TDM Service Bit. This bit is set if any of the above status bits<8:4> is set.
Reserved
10
R/O
Reserved. Always read as ‘0’.
CORSIGA
11
R/O
CORSIGA pin’s current logic level. Undefined at reset.
CORSIGB
12
R/O
CORSIGB pin’s current logic level. Undefined at reset.
CORSIGC
13
R/O
CORSIGC pin’s current logic level. Undefined at reset.
CORSIGD
14
R/O
CORSIGD pin’s current logic level. Undefined at reset.
CORSIGE
15
R/O
CORSIGE pin’s current logic level. Undefined at reset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
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