- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383644 > MT90500 (Mitel Networks Corporation) Multi-Channel ATM AAL1 SAR PDF資料下載
參數(shù)資料
| 型號： | MT90500 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動柜員機(jī)AAL1特區(qū) |
| 文件頁數(shù)： | 32/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁
MT90500
32
4.1.2
TDM Interface Operation
4.1.2.1
Main TDM Bus Operation
The main TDM bus (pins ST[15:0]) supports SCSA, MVIP, H-MVIP, ST-BUS, and IDL protocols. These buses
have different frame sync pulse orientations and different data sampling specifications, as well as different pin
requirements. However, all of these buses are composed of 16 data pins, as well as CLKx2, CLKx1, and
FSYNC lines.
The TDM bus type is controlled by the TDM Bus Type Register at 6010h. In all bus types, outputs change on
the rising edge of CLKx1. Inputs can be sampled at the 2/4, 3/4 or 4/4 point of the CLKx1 signal. MVIP/SCSA/
ST-BUS all use a negative FSYNC that is asserted for one CLKx2 cycle, straddling the frame boundary. The
IDL bus uses a positive FSYNC which is asserted for one cycle of CLKx1, preceding the frame boundary. (See
Figure 39, “Nominal TDM Bus Timing,” on page 114.)
4.1.2.2
TDM Loopback
The General Output Enable bit (GENOE in the TDM Interface Control Register at 6000h) is used to enable data
to be driven out on the TDM output streams. When this bit it not set (i.e. it is LOW), the internal TDM transmit
buses are connected to the internal TDM receive buses (while the internal TDM buses are disconnected from
the external TDM buses) giving a TDM loopback from ATM receive back to ATM transmit. In this mode, the
internally-generated TDM clocks and synchronization signals are used. This allows the user to test the
MT90500 in stand-alone mode by passing receive ATM cells through the SAR, through the internal loopback at
the TDM interface, and back through the SAR and out as transmit ATM cells.
4.1.2.3
Per-channel Output Enable Feature
The ST[15:0] pins are bidirectional, and are able to switch between input and output directions on a per-
channel basis. The Output Enable Registers located at addresses 7000 + 2N (N = 0, 1, ..., 127) are used for
individual time slot output enable control. Depending on the TDM bus rate, up to 128 registers (256 bytes) are
used to provide up to 2048 individual channel-output-enable bits. At 2.048 Mbps, 32 registers are used; at
4.096 Mbps, 64 registers are used; and at 8.192 Mbps, 128 registers are used.
During each channel period (TDM time slot), 16 output enable bits (one register) are read from the Output
Enable Registers. Within each frame, 32, 64, or 128 registers are read (depending on the TDM bus rate). The
GENOE bit must be set HIGH, as well as the individual channel-output-enable bit, in order for a TDM channel
to be transmitted from the MT90500 onto the TDM bus. In order to prevent data collisions on the TDM bus, the
user should clear all Output Enable Register bits for channels not used as outputs, prior to setting the GENOE
bit. The GENOE signal, when inactive, asynchronously deactivates the tristate buffers on the data pins and
routes the output paths back into the input paths, causing the TDM bus to enter the TDM Loopback mode (see
Section 4.1.2.2).
Since the ST pins are bidirectional, the input sampling is always active and output data can be re-sampled back
into the MT90500. This re-sampling is used when LOCSTi channels are output on a ST pin and then re-
sampled for ATM transmission, when ST outputs are re-sampled for transfer to the LOCSTo pin, or for test and
verification purposes.
4.1.2.4
Local Bus Operation
The local bus signals are:
LOCx2, LOCx1, LSYNC - clock output signals;
LOCSTi, LOCSTo - Local Serial TDM data in and data out.
The MT90500 provides three output clocks for the local TDM bus: LOCx2, LOCx1 and LSYNC. These clocks
are derived from CLKx2, and controlled by the relevant bits in the Local Bus Type Register (register 6020h).
The LCLKDIV bits allow LOCx2 to be equal to CLKx2, CLKx2 / 2, or CLKx2 / 4 (note that the local bus rate is
2.048 Mbps, which is always equal to, or less than, the main TDM bus rate). Also in register 6020h are the
control bits to select the LSYNC frame-pulse type, the routing of TDM streams onto and from the local bus, and
the LOCSTi sampling point.Except for the rate, the local bus type can be configured independently of the main
TDM bus type.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90500AL | Multi-Channel ATM AAL1 SAR |
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multi-Channel ATM AAL1 SAR |
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。