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MT90500
91
5.2.3
RX_SAR Registers
Table 26 - RX_SAR Control Register
Address: 3000 (Hex)
Label: RXSCR
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
APEMS
0
R/W
AAL1-byte Parity Error Misc. Select. When this bit is set, a parity error in the AAL1-byte
increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR
Misc. Event ID Register (3010h).
ACEMS
1
R/W
AAL1-byte CRC Error Misc. Select. When this bit is set, a CRC error in the AAL1-byte
increments the RX_SAR Misc. Event Counter Register (3012h) and affects the RX_SAR
Misc. Event ID Register (3010h).
SNEMS
2
R/W
AAL1 Sequence Number Error Misc. Select. When this bit is set, a sequence number error
in the AAL1-byte increments the RX_SAR Misc. Event Counter Register (3012h) and
affects the RX_SAR Misc. Event ID Register (3010h).
PPEMS
3
R/W
Pointer-byte Parity Error Misc. Select. When this bit is set, a parity error in the pointer-byte
(for P-Type cells only) increments the RX_SAR Misc. Event Counter Register (3012h) and
affects the RX_SAR Misc. Event ID Register (3010h).
POREMS
4
R/W
Pointer-byte Out of Range Error Misc. Select. When this bit is set, an out of range pointer-
byte (for P-Type cells only) increments the RX_SAR Misc. Event Counter Register (3012h)
and affects the RX_SAR Misc. Event ID Register (3010h).
APEIE
5
R/W
AAL1-byte Parity Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’
on APE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h.
ACEIE
6
R/W
AAL1-byte CRC Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’
on ACE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
SNEIE
7
R/W
AAL1-byte Sequence Number Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on SNE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register
0002h
PPEIE
8
R/W
Pointer-byte Parity Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a
‘1’ on PPE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
POREIE
9
R/W
Pointer-byte Out of Range Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on PORE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register
0002h
WUREIE
10
R/W
Write Underrun Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’
on WURE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
WOREIE
11
R/W
Write Overrun Error Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’ on
WORE in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
MCRIE
12
R/W
Misc. Counter Rollover Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When enabled, a ‘1’
on MCR in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register 0002h
WURCRIE
13
R/W
Write UnderRun Counter Rollover Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on WURCR in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register
0002h
WORCRIE
14
R/W
Write Overrun Counter Rollover Interrupt Enable. ‘0’ = Disabled; ‘1’ = Enabled. When
enabled, a ‘1’ on WORCR in Register 3002h will force a ‘1’ on RX_SAR_SERV in Register
0002h
TESTS
15
R/W
Test Status. When HIGH, this bit forces all the status events in the RX_SAR Status
Register at 3002h to occur. Also increments the RX_SAR Misc. Event Counter Register
(3012h), the RX_SAR Underrun Event Counter (3022h), and the RX_SAR Overrun Event
Counter (3032h) and affects the contents of the RX_SAR Misc. Event ID Register (3010h),
the RX_SAR Underrun Event ID Register (3020h), and the RX_SAR Overrun Event ID
Register (3030h). Used for test purposes only.