參數(shù)資料
型號： MT90500AL
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR
中文描述： 多通道自動柜員機AAL1特區(qū)
文件頁數(shù)： 101/159頁
文件大?。?/td> 514K
代理商： MT90500AL
MT90500
101
Table 50 - TDM Bus Type Register
Address: 6010 (Hex)
Label: TDMTYP
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
TDMFS
1:0
R/W
TDM Fsync type.
“00” = negative polarity for half-cycle of CLKx1, straddling the frame boundary (SCSA/
MVIP/H-MVIP/ST-BUS);
“01” = Reserved;
“10” = Reserved;
“11” = positive polarity for full-cycle of CLKx1, preceding the frame boundary (IDL).
When using the positive polarity frame sync, the MT90500 must be in Master mode, or
TCLKSYN (bit<6>) should be LOW, and the SC bus HDLC access will not function (pins
MC, MCRX, MCTX and MCCLK).
TDMSMPL
3:2
R/W
TDM Sampling. Determines the sampling point of the serial input bit.
“00” = 4/4;
“01” = 3/4;
“10” = 2/4;
“11” = Reserved.
TDMCLK
5:4
R/W
TDM Clock speed. Determines the data rate of the TDM bus (and CLKX1).
“00” = 2 MHz, 32 time slots/frame;
“01” = 4 MHz, 64 time slots/frame;
“10” = 8 MHz, 128 time slots/frame;
”11” = Reserved.
TCLKSYN
6
R/W
Selects source for internal CLKx1.
‘0’ = normal CLKx1 output operation as TDM Master, normal CLKx1 input operation as
TDM Slave;
‘1’ = derive CLKx1 from CLKx2 (Slave mode where no CLKx1 is provided by TDM bus)
Note that in TDM Slave mode, with TCLKSYN = ‘1’, the CLKx1 pin is not used as an output
but remains high-impedance. The CABS bit in register 6002h will therefore report a loss of
clocks unless an external signal is present at the CLKx1 pin.
CLKTYPE
7
R/W
Clock Type. Selects operation of CLKx2 Input when TDM Slave mode is selected (no
effect when TDM Master mode is selected).
‘0’ = single-ended input (one input pin: CLKx2);
‘1’ = differential input (two input pins: CLKx2PI and CLKx2NI).
CLKMASTER
8
R/W
TDM Clock Master.
‘0’ = MT90500 is TDM Slave, and does not drive TDM clock pins (CLKx2 is an input);
‘1’ = MT90500 is TDM Master, and drives the TDM clock pins (MT90500 drives CLKx2,
CLKx1, and FSYNC).
CLKALT
9
R/W
TDM Clock Alternate.
‘0’ = disabled;
‘1’ = MT90500 is designated as Clock Master Alternate
The Clock Master Alternate will become the Clock Master and drive the clock lines only if
the clock fail status bit (CFAIL in 6002h) is HIGH.
Note
: This bit is only used when
CORSIGACNF in 6004h is “11”, indicating that the CORSIGA pin is configured as
CLKFAIL input (SCSA mode).
Reserved
10
R/W
Reserved. Must always be set to ‘0’.
BUSHOLD
11
R/W
BUS Hold Time.
‘0’ = fast bus (SCSA 8 Mbps);
‘1’ = slow bus (MVIP / SCSA2 / IDL / ST-BUS)
Reserved
15:12
R/O
Reserved. Always read as “0000”.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
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