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參數(shù)資料
| 型號(hào)： | MT90500AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 78/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500AL |
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MT90500
78
4.7.3
Microprocessor Access and Device Reset
Upon hardware reset (using the RESET pin) of the MT90500, the microprocessor registers go to their
respective reset states, as indicated in the register descriptions. Further, the SRES bit in Register 0000h is set
LOW, “l(fā)atching” the reset state. No registers other than the Microprocessor Interface Registers can (nor
should) be accessed until the SRES bit is set HIGH. Steps to reset and restart the MT90500 are therefore:
1. Assert hardware RESET (and optionally TRISTATE), or write register 0000h to 0000h.
2. Remove hardware reset.
3. Allow at least 75 MCLK clock cycles (about 2
μ
sec at 60 MHz).
4. Write register 0000h to 4400h (enable normal internal clocks).
5. Write register 0000h to C400h (de-assert SRES).
6. Write register 0000h to desired functional setting.
7. Write other MT90500 registers. (Note that configuration bits must generally be programmed before
setting process enable bits.)
4.8
Test Interface
The MT90500 contains an IEEE 1149 standard Test Access Port (TAP), which provides Boundary-Scan test
access to aid board-level testing. (IEEE 1149 is often referred to by its older designation: JTAG - Joint Test
Action Group.)
4.8.1
Test Access Port
The test port is a standard IEEE 1149 interface, with the optional TRST pin. The Test Access Port consists of 5
pins:
TCLK
: Boundary-scan Test Clock.
TDI
: Test Data In; input pin clocked in on the rising edge of TCK. TDI should be pulled HIGH if bound-
ary-scan is not in use.
TDO
: Test Data Out; output pin updated on the falling edge of TCK. The output is in high-impedance
except when data is actually being shifted out.
TMS
: Test Mode Select; input control line clocked in on the rising edge of TCK. TMS should be pulled
HIGH if boundary-scan is not in use.
TRST
: Test Reset; asynchronous, active-low, input which is used to reset the JTAG interface, and the
TAP controller. The TRST pin has an internal pull-down, and should also be pulled LOW externally
whenever boundary-scan is not in use, to ensure normal operation of the MT90500. Figure 37 below
shows a typical board-level design, including how TRST can be pulled HIGH by the test connector in
cases where the tester does not provide a TRST pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
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