參數(shù)資料
型號： MT90500AL
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR
中文描述： 多通道自動柜員機AAL1特區(qū)
文件頁數(shù)： 21/159頁
文件大小： 514K
代理商： MT90500AL
MT90500
21
Table 4 - External Memory Interface Pins
Pin #
Pin Name
I/O
Type
Description
98
MEMCLK
O
3.3V, 4mA
Memory Clock. Internally connected to MCLK.
147
MEM_CS0L
O
3.3V, 4mA
Active LOW memory chip select signal. This chip select is used in all memory
modes. When there are two chips per bank, MEM_CS0L is associated with
MEM_DAT[15:0] of Bank 0.
176
MEM_CS0H
O
3.3V, 4mA
Active LOW memory chip select signal. This chip select is used when there
are two 16-bit memory chips per bank. MEM_CS0H is associated with
MEM_DAT[31:16] of Bank 0.
148
MEM_CS1L
O
3.3V, 4mA
Active LOW memory chip select signal. This chip select is used when there
are two banks and two chips per bank. MEM_CS1L is associated with
MEM_DAT[15:0] of Bank 1.
177
MEM_CS1H
O
3.3V, 4mA
Active LOW memory chip select signal. This chip select is used when there
are two banks and two chips per bank. MEM_CS1H is associated with
MEM_DAT[31:16] of Bank 1.
178, 179, 149,
150
MEM_WR[3:0]
O
3.3V, 4mA
Active
MEM_DAT[31:24];
MEM_WR[1] is associated with MEM_DAT[15:8]; MEM_WR[0] is associated
with MEM_DAT[7:0].
LOW
byte-write
MEM_WR[2] is associated with MEM_DAT[23:16];
enables.
MEM_WR[3]
is
associated
with
180
MEM_OE
O
3.3V, 4mA
Active LOW output enable.
123, 122, 121,
118, 117, 116,
115, 103, 102,
99, 146, 144,
130, 128, 127,
126, 125, 124
MEM_ADD[17:0]
O
3.3V, 4mA
Memory address lines.
166, 167, 168,
170, 171, 173,
174, 175, 153,
154, 155, 156,
158, 159, 162,
164, 133, 134,
135, 136, 137,
138, 142, 143,
105, 106, 107,
108, 109, 112,
113, 114
MEM_DAT[31:0]
I/O
3.3V CMOS
PU / 3.3V 4mA
Memory
MEM_DAT[23:16] represent the upper-middle byte; MEM_DAT[15:8]
represent the lower-middle byte; MEM_DAT[7:0] represent the lower byte.
data
lines.
MEM_DAT[31:24]
represent
the
upper
byte;
165, 152, 131,
104
MEM_PAR[3:0]
I/O
3.3V CMOS
PU / 3.3V 4mA
Memory parity lines. MEM_PAR[3:0] are the optional “parity” bits that allow
TDM Read Underrun detection. MEM_PAR[3] is related to MEM_DAT[31:24],
MEM_PAR[2] is related to MEM_DAT[23:16], MEM_PAR[1] is related to
MEM_DAT[15:8], and MEM_PAR[0] is related to MEM_DAT[7:0]. When
unused, these pins must be pulled up via external resistors.
Note:
MT90500 3.3 V CMOS inputs are pulled up to the 3.3 Volt rail. See Table 76 on page 112.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
MT90502 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
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MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
MT90503 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR
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