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MT90500
18
TDM Read Underrun Error Interrupt
TDM Read Underrun Counter Rollover Interrupt
2.8.6
Timing Module Interrupts
8 kHz Reference Failure Interrupt
SRTS TX Underrun Interrupt
SRTS TX Overrun Interrupt
SRTS RX Underrun Interrupt
SRTS RX Overrun Interrupt
Adaptive Clock Loss of Timing Reference Cell Interrupt
Adaptive Clock Loss of Synchronization Interrupt
2.9
Statistics
The MT90500 provides a number of statistics to allow monitoring of the MT90500. These statistics generally
parallel the operation of some of the interrupt source bits. The counters (except the Timing Recovery counters)
also set rollover interrupt source bits when they reach their terminal counts and return to zero.
2.9.1
RX_SAR Statistics
Miscellaneous Event Counter: This 16-bit register’s value is incremented each time a (mask-
selected) miscellaneous error occurs.
AAL1-byte Parity Error
AAL1-byte CRC Error
AAL1 Sequence Number Error
Pointer-byte Parity Error
Pointer-byte Out of Range Error
Miscellaneous Event ID Register: The address of the RX Control Structure that caused the last
miscellaneous error.
Underrun Count: This 16-bit register’s value is incremented each time a CBR Receive Underrun
occurs.
Underrun ID Number: The address of the RX Control Structure that caused the last underrun
error.
Overrun Count: This 16-bit register is incremented each time a CBR Receive Overrun occurs.
Overrun ID Number: The address of the RX Control Structure that caused the last overrun error.
2.9.2
TDM Statistics
TDM Read Underrun Time Slot Stream. Contains the time slot and stream on which the last TDM
read underrun was detected.
TDM Read Underrun Counter. Each time a TDM read underrun occurs, this register’s value is
incremented.
2.9.3
Timing Recovery Statistics
Event Counter: Counts the reception of timing reference cells or 8 kHz markers.
CLKx1 Counter: 24-bit counter which keeps a running count of TDM byte-periods.