參數(shù)資料
型號： MT90500AL
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR
中文描述： 多通道自動柜員機(jī)AAL1特區(qū)
文件頁數(shù)： 24/159頁
文件大小： 514K
代理商： MT90500AL
MT90500
24
Table 7 - Reset State of I/O and Output Pins
Pin Name
I/O
Reset State
Additional Control Information
PTXDATA[7:0]
O
Active during and after reset.
N / A
PTXPAR
O
Active during and after reset.
N / A
PTXCLK
I/O
High-impedance
The PTXCLK_SEL bits in the Main Control Register (0000h) are LOW
after reset; PTXCLK is tristated and an input.
PTXEN
O
Active during and after reset.
N / A
PTXSOC
O
Active during and after reset.
N / A
STXCLAV
O
Active during and after reset.
N / A
MEMCLK
O
Continues to drive at MCLK
rate during reset.
N / A
MEM_CS[1:0][H:L]
O
Active during and after reset.
N / A
MEM_WR[3:0]
O
Active during and after reset.
N / A
MEM_OE
O
Active HIGH during reset.
RESET LOW forces this pin HIGH. After reset, this pin goes LOW.
MEM_ADD[17:0]
O
Active during and after reset.
N / A
MEM_DAT[31:0]
I/O
High-impedance
N / A
MEM_PAR[3:0]
I/O
High-impedance
N / A
RDY/DTACK
O
Active during and after reset.
Tristated when CS is HIGH.
In Motorola mode, pin drives HIGH during reset. In Intel mode, drives LOW
during reset.
INT
O
High-impedance
The interrupt enable bits in the Main Control Register at 0000h are reset to
zero; interrupts are masked after reset.
D[15:0]
I/O
High-impedance
N / A
TDO
O
Determined by TRST and / or
TAP controller state
N / A
ST[15:0]
I/O
High-impedance
The GENOE bit in the TDM Interface Control Register (6000h) is LOW
after reset; these TDM data pins are tristated and in loopback mode.
CLKx1
I/O
Input
The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to ‘0’;
the MT90500 is TDM Slave, and CLKx1 is input from the TDM bus.
FSYNC
I/O
Input
The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to ‘0’;
the MT90500 is TDM Slave and FSYNC is input from the TDM bus.
CORSIGA/
CLKFAIL
I/O
Input
The TDM I/O Register at 6004h resets to all zeroes; all CORSIGxCNF are
set to “00” and all CORSIGx pins are configured as inputs.
CORSIGB / MC /
FNXI
I/O
Input
See CORSIGA.
CORSIGC / MCTX /
SRTSENA
I/O
Input
See CORSIGA.
CORSIGD / MCRX /
SRTSDATA
I/O
Input
See CORSIGA.
CORSIGE
/ MCCLK
I/O
Input
See CORSIGA.
SEC8K
I/O
Input
The SEC8KEN bit in the Master Clock Generation Control Register
(6090h) resets to ‘0’; SEC8K is an input.
REF8KCLK
O
Active during and after reset.
Due to the reset values of the Master Clock Generation Control Register
(6090h) and the Master Clock / CLKx2 Division Factor (6092h),
REF8KCLK is initially equal to MCLK / 8194.
FREERUN
O
Active HIGH during and after
reset.
The FREERUN bits in the Master Clock Generation Control Register at
6090h are “00” after reset; the FREERUN pin is reset to active HIGH.
LOCx2
O
Active during and after reset.
N / A
LOCx1
O
Active during and after reset.
N / A
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
MT90502 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
MT90503 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR
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