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參數(shù)資料
| 型號： | MT90500AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動柜員機AAL1特區(qū) |
| 文件頁數(shù)： | 28/159頁 |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500AL |
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MT90500
28
4.
Functional Description
As shown in Figure 1, “MT90500 Block Diagram,” on page 12, the MT90500 device consists of the following
major components: TDM Module, External Memory Controller, TX_SAR, RX_SAR, UTOPIA Module, Clock
Recovery, Microprocessor Interface, and Test Interface. This section describes each module in detail.
4.1
TDM Module
This circuit module is the interface to the Time Division Multiplexed (TDM) buses, which carry N x 64kbps data.
The TDM module interfaces are:
16 bidirectional TDM data streams on pins ST[15:0]; these pins can be configured through soft-
ware registers to support various bus formats (ST-BUS, MVIP, H-MVIP, SCSA, or IDL) and data
rates of 2.048 Mbps, 4.096 Mbps, or 8.192 Mbps; (For the selection of the bus type, see TDM Bus
Type Register at address 6010h in Section 5.)
the TDM bus clocks (CLKx2, CLKx1) and frame synchronization signal (FSYNC);
the TDM bus ancillary signals such as SEC8K (MVIP) and CLKFAIL (SCSA);
a local TDM bus (LOCx2, LOCx1, LSYNC, LOCSTi, and LOCSTo); the format of the bus, which
runs at 2.048 Mbps (LOCx2 = 4.096 Mbps), is user-programmable via software (see Local Bus
Type Register at address 6020h).
The TDM module moves TDM data from the TDM serial inputs to the external memory (where it is read by the
TX_SAR) in the transmit direction, and from the external memory (where it was written by the RX_SAR) to the
TDM outputs in the receive direction. This is done with the aid of an internal TDM frame buffer, which is used to
buffer 4 frames of each TDM channel in both directions; i.e. four frames in the receive direction (ATM to TDM),
and four frames in the transmit direction (TDM to ATM). The TDM module can be divided into four main
processes:
TDM Clock Logic, which controls all the operations related to clock generation and clock signal
monitoring on the TDM bus;
TDM Interface Operation, which controls the input and output of the serial TDM data;
TDM Data to External Memory Process, which transfers TDM input data into Transmit Circular
Buffers in the external memory;
External Memory to TDM Data Output Process, which transfers TDM output data from Receive
Circular Buffers in the external memory to the TDM output bus.
Each of these processes are described in detail below.
4.1.1
TDM Clock Logic
The TDM Clock Logic controls all of the operations related to clock generation and clock signal monitoring on
the TDM bus. The block diagram of the TDM Clock Logic is shown in Figure 3. This module consists of several
blocks, including: selection logic for an 8 kHz reference for the external PLL (REF8KCLK), the main TDM bus
clock generation logic, the local TDM bus clock generation logic, the clock drivers & clock selection for the
SEC8K signal, and the clock failure detection logic.
4.1.1.1
TDM Timing Modes
The MT90500 supports 4 major TDM timing modes. There are also a number of TDM timing features which are
independent of the TDM timing mode being used:
The SEC8K pin (MVIP compatibility) can be programmed as either output or input. The SEC8KEN
bit in the MCGCR Register (6090h) enables the SEC8K pin driver. If the SEC8K pin is enabled as
an output, the SEC8KSEL bit in the same register selects the source for this signal (the EX_8KA
input, or the internal 8 kHz FS_INT signal which is derived from CLK16).
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相關代理商/技術參數(shù) |
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| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
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| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
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