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MT90500
95
Table 36 - VPI / VCI Concatenation Register
Address: 4010 (Hex)
Label: VPVCC
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
N
4:0
R/W
The N least significant bits of the VCI to be used as an address in the VC look-up table.
M
7:5
R/W
The M least significant bits of the VPI to be used as an address in the VC look-up table.
Reserved
8
R/W
Reserved. Must be written as ‘0’.
Reserved
15:9
R/O
Reserved. Always read as “0000_000”.
The VC search mechanism uses a table that can have up to 32K double-word (32-bit) entries. The table can therefore be 128 Kbytes long.
This requires a 17-bit offset pointer formed by adding two least significant zeroes to a base 15-bit pointer. The base 15-bit pointer is formed
by concatenation of the N least significant bits of the VCI with the M least significant bits of the VPI. The sum of M+N must be at least 8 and
a maximum of 15
.
If M+N < 15, the most significant bits are zeroed.
Example: assume N=8, indicating that the 8 LSBs of the VCI will be used to form the least significant part of the pointer. Assume M=4,
indicating that the 4 LSBs of the VPI will be used to form the most significant portion of the pointer. Since M+N = 12 < 15, bits<14:12> of the
base pointer will be zeroed. Assume the receive VPI value is 23h and the receive VCI value is 5678h. The resulting base 15-bit pointer will
be “0378.” When two least significant ‘0’ bits are added to form a 17-bit pointer, the result is 00DE0h. This value is added to the Look-up
Table Base Address Register (401Eh) contents to form a 21-bit address than can be located anywhere in memory.
Table 37 - VPI Match Register
Address: 4012 (Hex)
Label: VPMT
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
VPIMATCH
7:0
R/W
VPI Match value. VPI of received cells are compared to the value in this register to see if
the cells should be passed to the internal FIFO, or discarded.
Reserved
15:8
R/O
Reserved. Always read as 00h.
Note:
Set the VPI Match and Mask filter as narrowly as practical for the application. See Receive Cell Selection Process on page 63.
Table 38 - VPI Mask Register
Address: 4014 (Hex)
Label: VPMS
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
VPIMASK
7:0
R/W
VPI Mask value. Each bit, when set, enables the comparison of the cell VPI and the
VPIMATCH field. If a bit in this register is not set, the corresponding bit in the received cell
VPI is considered valid, regardless of the setting in the VPIMATCH field.
Reserved
15:8
R/O
Reserved. Always read as 00h.
Table 39 - VCI Match Register
Address: 4016 (Hex)
Label: VCMT
Reset Value: 0000 (Hex)
Label
Bit Position
Type
Description
VCIMATCH
15:0
R/W
VCI Match value. VCI of received cells are compared to the value in this register to see if
the cells are valid.
Note:
Set the VCI Match and Mask filter as narrowly as practical for the application. See Receive Cell Selection Process on page 63.