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參數(shù)資料
| 型號(hào)： | MT90500AL |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 105/159頁(yè) |
| 文件大?。?/td> | 514K |
| 代理商： | MT90500AL |
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MT90500
105
OUT_SYNC_IE
6
R/W
Out-Of-Sync Interrupt Enable - Timing Reference Cell Sub-Module. When enabled, a ‘1’ on
OUT_SYNC in Register 6082h will force a ‘1’ on TIM_SERV in Register 0002h.
TIM_ENA
7
R/W
Timing Enable - When ‘1’, enables the operation of the Timing Reference Cell Sub-Module
receive circuit for Adaptive Clock Recovery.
Reserved
15:8
R/O
Will always read 00h.
Table 60 - Clock Module General Status Register
Address: 6082 (Hex)
Label: CMGSR
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
REFFAIL
0
R/O/L
Reference Clock Failure - Clock Generation Sub-Module. When ‘1’, indicates that the
REF8KCLK signal has failed. When this bit is ‘1’ and the FREERUN bits in the Master
Clock Generation Control Register (MCGCR at 6090h) are “01”, the external signal
FREERUN will be activated.
MCLK should be at least 2048 times the REF8KCLK
frequency for proper operation.
Writing a ‘1’ over this bit will clear it.
SRTST_UND
1
R/O/L
SRTS Transmit Underrun - SRTS Sub-Module. When ‘1’, indicates a slip underrun error
has occurred in the SRTS transmit circuit. This means that the TX_SAR (scheduler) is
sending RTSs faster than the SRTS Transmit Divider Register is generating them. Check
the scheduler vs. registers 60B0h, and 60B2h. Can be ignored when SRTS transmission is
not enabled. Writing a ‘1’ over this bit will clear it.
SRTST_OVR
2
R/O/L
SRTS Transmit Overrun - SRTS Sub-Module. When ‘1’, indicates a slip overrun error has
occurred in the SRTS transmit circuit. This means that the SRTS Transmit Divider Register
is generating RTSs faster than the TX_SAR (scheduler) is sending them. Check the
scheduler vs. registers 60B0h, and 60B2h. Can be ignored when SRTS transmission is not
enabled. Writing a ‘1’ over this bit will clear it.
SRTSR_UND
3
R/O/L
SRTS Receive Underrun - SRTS Sub-Module. When ‘1’, indicates a slip underrun error has
occurred in the SRTS receive circuit. This means that the RX_SAR is receiving RTSs faster
than the SRTS Transmit Divider Register is generating RTSs. Check registers 60B4h, and
60B6h. Can be ignored when SRTS reception is not enabled. Writing a ‘1’ over this bit will
clear it.
SRTSR_OVR
4
R/O/L
SRTS Receive Overrun - SRTS Sub-Module. When ‘1’, indicates a slip overrun error has
occurred in the SRTS receive circuit. This means that the SRTS Transmit Divider Register
is generating RTSs faster than the RX_SAR is receiving RTSs. Check registers 60B4h, and
60B6h. Can be ignored when SRTS reception is not enabled. Writing a ‘1’ over this bit will
clear it.
LOSS_TIMRF
5
R/O/L
Loss of Timing Reference Cell stream - Timing Reference Cell Sub-Module. When ‘1’,
indicates a loss of timing reference cells (or marker) event has occurred (loss period
determined by Time-out field at 60A0h) while the Adaptive Clock Recovery state machine
was enabled (TIM_ENA bit set in Clock Module General Control Register at 6080h). Writing
a ‘1’ over this bit will clear it.
OUT_SYNC
6
R/O/L
Out-Of-Sync - Timing Reference Cell Sub-Module. When ‘1’, indicates the Timing
Reference Cell state machine went out of sync.
This bit is set only when the state
machine initially goes out of sync - if it stays out of sync., this bit will be cleared.
Writing a ‘1’ over this bit will clear it.
Reserved
14:7
R/O
Will always read “000_0000_0”.
TIME_SERV
15
R/O
This bit is set if any of bits<6:0> are set.
Note:
Bits<6:0> will be set if the TESTS bit is set in the TDM Interface Control Register at 6000h.
Table 59 - Clock Module General Control Register
Address: 6080 (Hex)
Label: CMGCR
Reset Value: 0000 (Hex)
Label
Bit
Position
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90502 | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）) |
| MT90732AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90732 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
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