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參數(shù)資料
| 型號(hào)： | MT90500AL |
| 廠(chǎng)商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel ATM AAL1 SAR |
| 中文描述： | 多通道自動(dòng)柜員機(jī)AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 23/159頁(yè) |
| 文件大小： | 514K |
| 代理商： | MT90500AL |
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MT90500
23
Table 6 - TDM Port Pins
Pin #
Pin Name
I/O
Type
Description
25, 23, 22, 19,
18, 17, 15, 14,
12, 11, 10, 9,
8, 6, 5, 4
ST[15:0]
I/O
TTL PU /
5V, 12mA SR
TDM data streams. Used to pass PCM (voice) bytes or other data types. In
order to enable any of these pins as outputs, the GENOE bit in the TDM
Interface Control Register (6000h) must be set, as well as the appropriate
channel bits in the Output Enable Registers.
230
CLKx2PI
I
Diff +
Differential clock signal input (+) running at twice the serial TDM data
stream frequency. This pin is used only in differential clock mode (H-MVIP)
and should be tied HIGH when not in use. For normal (non-differential)
clock mode input, use CLKx2/CLX2PO pin.
227
CLKx2NI
I
Diff -
Differential clock signal input (-) running at twice the serial TDM data
stream frequency. This pin is used only in differential clock mode (H-MVIP)
and should be grounded when not in use.
233
CLKx1
I/O
TTL PU /
5V, 12mA SR
Clockx1. This signal represents the CLKx2 signal divided by 2.
232
FSYNC
I/O
TTL PU /
5V, 12mA SR
Frame sync. Bidirectional 8 kHz reference to/from main TDM Bus.
30
IC
I
TTL PU
Internal connection (must be HIGH).
32
CORSIGA /
CLKFAIL
I/O
TTL PU /
5V, 12mA SR
CORSIGA I/O when not used by the TDM bus. Clock fail on SCSA bus.
235
CORSIGB / MC /
FNXI
I/O
TTL PU /
5V, 12mA SR
CORSIGB I/O when not used by the TDM bus. Message Channel (I/O) on
the SCSA bus. SRTS FNX Network Clock Input - this input line is required
when SRTS clock recovery mode is used.
Note:
When used for clock
recovery, this clock must be < MCLK / 3.
33
CORSIGC /
MCTX /
SRTSENA
I/O
TTL PU /
5V, 4mA SR
CORSIGC I/O when not used by the TDM bus. Message Channel Transmit
(input) toward SCSA bus from HDLC controller. This signal represents
SRTS ENA output when SRTS clock recovery mode is selected.
34
CORSIGD /
MCRX /
SRTSDATA
I/O
TTL PU /
5V, 4mA SR
CORSIGD I/O when not used by the TDM bus. Message Channel Receive
(output) from SCSA bus toward HDLC controller. This signal represents
SRTS DATA output serial line when SRTS clock recovery mode is
selected.
35
CORSIGE /
MCCLK
I/O
TTL PU /
5V, 4mA SR
CORSIGE I/O when not used by the TDM bus. Message Channel HDLC
controller clock (output) from the SCSA bus.
83
EX_8KA
I
TTL PU
An 8 kHz clock input that can be used as reference in the generation of the
REF8KCLK or SEC8K lines.
234
SEC8K
I/O
TTL PU /
5V, 12mA
Secondary alternate 8 kHz clock. Compatible with MVIP and H-MVIP
modes.
226
REF8KCLK
O
5V, 12mA SR
An 8 kHz clock generated internally. This signal is generated from one of
several internal sources which are programmed by the user. This output
can provide a reference clock to an external PLL to generate the 16.384 /
32.768 MHz required for the operation of the IC in master mode.
224
PLLCLK
I
TTL PU
16.384 / 32.768 MHz TDM clock reference from external PLL.
31
FREERUN
O
5V, 12mA SR
Active HIGH external PLL freerun indication.
236
LOCx2
O
5V, 4mA SR
Local TDM Bus Clockx2.
3
LOCx1
O
5V, 4mA SR
Local TDM Bus Clockx1.
28
LSYNC
O
5V, 4mA SR
Local TDM Bus Frame Sync.
26
LOCSTo
O
5V, 4mA SR
Local TDM Bus Serial Data Out Stream.
27
LOCSTi
I
TTL PU
Local TDM Bus Serial Data In Stream.
231
CLKx2/
CLKx2PO
I/O
TTL PU /
5V, 12mA
CLKx2 Input/Output / CLKx2 Positive Output. Normal (non-differential)
CLKx2 input in TDM Clock Slave mode. CLKx2 output (differential and non-
differential) in TDM Clock Master mode.
228
CLKx2NO
O
5V, 12mA
CLKx2 Negative Output. Differential negative output clock. (Inverse of
CLKx2PO). Used in TDM Clock Master, differential clock mode (H-MVIP);
active whenever MT90500 is TDM Clock Master. (Leave unconnected if
non-differential clock desired.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90500AL-ENG1 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90502 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502_06 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
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