參數(shù)資料
型號： MT90500AL
廠商： Mitel Networks Corporation
英文描述： Multi-Channel ATM AAL1 SAR
中文描述： 多通道自動柜員機AAL1特區(qū)
文件頁數(shù)： 50/159頁
文件大小： 514K
代理商： MT90500AL
MT90500
50
4.3.2.2
Transmit Control Structures
Within each frame within a transmit event scheduler 8, 16, or 32 VC Pointers can be programmed. Each entry
represents a request to the hardware to generate a cell on that VC. An entry can be active or not, depending on
the T bits located in the three LSBs of the entry word. An inactive entry is skipped. An active entry either tells
the hardware to transmit the next non-CBR data cell held in the Transmit Data Cell FIFO in the external
memory, (as explained in Section 4.3.3) or to transmit a CBR cell characterized by the Transmit Control
Structure at the address pointed to by “TX_Struct_Pnt”. This latter process will be outlined in this section.
Once an active CBR VC Pointer is found in the event scheduler, the TX_SAR reads the Transmit Control
Structure (Figure 16 for CBR-AAL0 and AAL1 type cells, Figure 17 for CBR-AAL5 type cells) and may either
send a cell or not. The ‘A’ bit in the Transmit Control Structure indicates whether the structure is active (an
inactive structure will never generate a cell). When opening a VC, this three step procedure must always be
followed: first, the software must write the Transmit Control Structure into the memory and clear both the ‘A’
and ‘S’ bits in that structure; second, all events pointing to the Transmit Control Structure must be written in the
event scheduler; finally, the ‘A’ bit must be set by the software. This procedure forces the hardware to ignore all
events pointing to a Transmit Control Structure until its ‘A’ bit is set. When the ‘A’ bit is set, all scheduler events
for this VC immediately become active and the transmission process for this VC is enabled. Please refer to the
MT90500 Programmers’ Manual, for detailed information on setting up a VC for the TDM to ATM Transmit
Process.
If the Transmit Control Structure has never been updated by the hardware, the “Circ. Buf. Pnt” field must
indicate “how old” (in terms of 125
μ
s TDM frames) the first byte in the first cell should be. For instance, if a cell
contains 47 bytes, and the age of the first byte to be sent is 46, the last byte to be sent in the cell will have an
AS
GFC /
VPI(11:8)
0
7
8
15
Last Entry
First Entry
Payload Size
Current Entry
PSEL
Offset
HEC
V
V
V
V
V
V
V
V
+00
+02
+04
+06
+08
+0A
+0C
+0E
+10
+12
+14
+16
+58
+5A
+5C
+5E
A
SEQ
Special Notes:
First Entry:
indicates location of the first TX Circular Buffer Address within the
Transmit Control Structure (lower bits are always 1000).
Note difference
between first entry location in CBR-AAL5 Transmit Control Structure and
AAL1/CBR-AAL0 Transmit Control Structure.
AS:
AAL Type. “00”= CBR-AAL5 (AAL5 cells are a special case of AAL0).
PSEL:
P-Byte Selection. “0000” for CBR-AAL5.
PTI:
LSB of field must be set to ‘1’ to identify this as a CBR-AAL5 type cell.
Circ. Buf. Pnt.
VPI(7:0)
VCI(15:12)
VCI(11:0)
PTI
Minimum Structure
Size - 18 bytes
Maximum Structure
Size - 96 bytes
R S 00
C1
Figure 17 - Transmit Control Structure Format (CBR-AAL5)
TX Circular Buffer Address
(bits<20:6>)
TX Circular Buffer Address
(bits<20:6>)
TX Circular Buffer Address
(bits<20:6>)
TX Circular Buffer Address
(bits<20:6>)
0000 0000 0000 0000
TX Circular Buffer Address
(bits<20:6>)
TX Circular Buffer Address
(bits<20:6>)
TX Circular Buffer Address
(bits<20:6>)
TX Circular Buffer Address
(bits<20:6>)
0000 0000 0000 0000
相關(guān)PDF資料
PDF描述
MT90502 Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設(shè)備（基于通訊總線的系統(tǒng)與ATM網(wǎng)絡(luò)的接口）)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90500AL-ENG1 制造商:Mitel Networks Corporation 功能描述:
MT90502 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR
MT90502AG 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述:
MT90503 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR
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