2
–
16
Table 2
–
14. CardBus PC Card Interface Control Terminals (Slots A and B)
TERMINAL
NUMBER
SLOT
A
NAME
SLOT
B
I/O
DESCRIPTION
GHK
GHK
CAUDIO
H17
V09
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1520
supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CBLOCK
N14
N03
I/O
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CCD1
CCD2
U11
G18
H05
P09
I
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and
CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type.
CDEVSEL
N15
P03
I/O
CardBus device select. The PCI1520 asserts CDEVSEL to claim a CardBus cycle as the target device.
As a CardBus initiator on the bus, the PCI1520 monitors CDEVSEL until a target responds. If no target
responds before timeout occurs, then the PCI1520 terminates the cycle with an initiator abort.
CFRAME
M15
R03
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When CFRAME is deasserted, the CardBus bus transaction is in the final data phase.
CGNT
P18
N05
O
CardBus bus grant. CGNT is driven by the PCI1520 to grant a CardBus PC Card access to the CardBus
bus after the current data transaction has been completed.
CINT
H19
V08
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the
host.
CIRDY
N18
P05
I/O
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
CPERR
R18
N06
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following the data cycle during which a parity error is
detected.
CREQ
K17
R07
I
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus
bus as an initiator.
CSERR
H18
W09
I
CardBus system error. CSERR reports address parity errors and other system errors that could lead
to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak
pullup; deassertion may take several CCLK periods. The PCI1520 can report CSERR to the system
by assertion of SERR on the PCI interface.
CSTOP
P17
P02
I/O
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that
do not support burst data transfers.
CSTSCHG
H14
U09
I
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as
a wake-up mechanism.
CTRDY
N17
R02
I/O
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and
CTRDY are asserted; until this time, wait states are inserted.
CVS1
CVS2
J15
L18
U08
P07
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.
Terminal name for slot A is preceded with A_. For example, the full name for terminals 140 and H18 is A_CAUDIO.
Terminal name for slot B is preceded with B_. For example, the full name for terminals 72 and V09 is B_CAUDIO.