參數(shù)資料
型號(hào)： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè)
文件頁數(shù)： 79/125頁
文件大小： 716K
代理商： PCI1520-EP
4
–
26
4.37 Power-Management Capabilities Register
This register contains information on the capabilities of the PC Card function related to power management. Both
PCI1520 CardBus bridge functions support D0, D1, D2, and D3 power states. See Table 4
–
14 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Power-management capabilities
Type
RW
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
Register:
Offset:
Type:
Default:
Power-management capabilities
A2h
Read/Write, Read-only
FE12h
Table 4
–
14. Power-Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
PME support. This 5-bit field indicates the power states from which the PCI1520 device functions may
assert PME. A 0 (zero) for any bit indicates that the function cannot assert the PME signal while in that
power state. These five bits return 11111b when read. Each of these bits is described below:
15
PME_Support
RW
Bit 15 defaults to the value 1 indicating the PME signal can be asserted from the D3cold state. This bit is
R/W because wake-up support from D3cold is contingent on the system providing an auxiliary power source
to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC
terminals for D3cold wake-up support, then BIOS should write a 0 to this bit.
Bit 14 contains the value 1, indicating that the PME signal can be asserted from D3hot state.
Bit 13 contains the value 1, indicating that the PME signal can be asserted from D2 state.
Bit 12 contains the value 1, indicating that the PME signal can be asserted from D1 state.
Bit 11 contains the value 1, indicating that the PME signal can be asserted from the D0 state.
14
–
11
PME_Support
R
10
D2_Support
R
D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device
power state.
9
D1_Support
R
D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device
power state.
8
–
6
RSVD
R
Reserved. Bits 8
–
6 return 0s when read.
5
DSI
R
Device-specific initialization. Bit 5 returns 1 when read, indicating that the CardBus controller function
requires special initialization (beyond the standard PCI configuration header) before the generic-class
device driver is able to use it.
4
AUX_PWR
R
Auxiliary power source. Bit 4 is meaningful only if bit 15 (PME_Support, D3cold) is set. When bit 4 is set,
it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way of a
proprietary delivery vehicle. When bit 4 is 0, it indicates that the function supplies its own auxiliary power
source.
3
PMECLK
R
PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the PCI1520 to
generate PME.
2
–
0
VERSION
R
Version. Bits 2
–
0 return 010b when read, indicating that the power-management registers (PCI offsets
A4h
–
A7h, see Sections 4.38
–
4.40) are defined in the
PCI Bus Power Management Interface Specification
version 1.1.
相關(guān)PDF資料
PDF描述
PCI1620GHK Controller Miscellaneous - Datasheet Reference
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PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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