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參數(shù)資料
| 型號： | PCI1520-EP |
| 英文描述： | Military Enhanced Plastic PC Card Controllers Data Manual |
| 中文描述： | 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 64/125頁 |
| 文件大?。?/td> | 716K |
| 代理商： | PCI1520-EP |
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4
–
11
4.20 Memory Limit Registers 0, 1
The memory limit registers indicate the upper address of a PCI memory address range. These registers are used
by the PCI1520 to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to PCI. Bits 31
–
12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11
–
0 are read-only and always return 0s. Write
transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
for the PCI1520 to claim any memory transactions through CardBus memory windows; that is, these windows are
not enabled by default to pass the first 4 Kbytes of memory to CardBus.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Memory limit registers 0, 1
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Memory limit registers 0, 1
Type
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Memory limit registers 0, 1
20h, 28h
Read-only, Read/Write
0000 0000h
4.21 I/O Base Registers 0, 1
The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the
PCI1520 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page, and the
upper 16 bits (31
–
16) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 31
–
2
are read/write. Bits 1 and 0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural
doubleword boundary.
NOTE:
Either the I/O base register or the I/O limit register must be nonzero to enable any I/O
transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
I/O base registers 0, 1
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
I/O base registers 0, 1
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
I/O base registers 0, 1
2Ch, 34h
Read-only, Read/Write
0000 0000h
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|---|---|
| PCI1620GHK | Controller Miscellaneous - Datasheet Reference |
| PCI1620PDV | Controller Miscellaneous - Datasheet Reference |
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| PCI2050GHK | BUS CONTROLLER |
| PCI2050PDV | BUS CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI1520GHK | 功能描述:外圍驅(qū)動器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PC CARD CONTROLLERS |
| PCI1520IGHK | 功能描述:外圍驅(qū)動器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520IGHKEP | 功能描述:外圍驅(qū)動器與原件 - PCI Mil Enhance PC Card Cntrlr Data Manual RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520IPDV | 功能描述:外圍驅(qū)動器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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