參數(shù)資料
型號(hào): PCI1520-EP
英文描述: Military Enhanced Plastic PC Card Controllers Data Manual
中文描述: 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè)
文件頁(yè)數(shù): 48/125頁(yè)
文件大?。?/td> 716K
代理商: PCI1520-EP
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3
20
The PCI1520 restarts the PCI clock using the CLKRUN protocol under any of the following conditions:
A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card.
A CardBus CBWAKE (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in either socket.
A CardBus attempts to start the CCLK using CCLKRUN.
A CardBus card arbitrates for the CardBus bus using CREQ.
3.8.3
CardBus PC Card Power Management
The PCI1520 implements its own card power-management engine that can turn off the CCLK to a socket when there
is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface
to control this clock management.
3.8.4
16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h/42h/802h, see Section 5.3) and PWRDWN
bit (bit 0) of the ExCA global control register (ExCA offset 1Eh/5Eh/81Eh, see Section 5.20) bits are provided for 16-bit
PC Card power management. The COE bit places the card interface in a high-impedance state to save power. The
power savings when using this feature are minimal. The COE bit resets the PC Card when used, and the PWRDWN
bit does not. Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function
when there is no card activity.
NOTE:
The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3.8.5
Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the PCI1520. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the PCI1520
in order to minimize power consumption.
Gating PCLK does not create any issues with respect to the power switch interface in the PCI1520. This is because
the PCI1520 does not depend on the PCI clock to clock the power switch interface. There are two methods to clock
the power switch interface in the PCI1520:
Use an external clock to the PCI1520 CLOCK terminal
Use the internal oscillator
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, then the PCI clock must be restarted in order to pass the interrupt, because neither the internal oscillator nor
an external clock is routed to the serial-interrupt state machine. Figure 3
15 is a signal diagram of the suspend
function.
相關(guān)PDF資料
PDF描述
PCI1620GHK Controller Miscellaneous - Datasheet Reference
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
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