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QuadFALC
TM
PEF 22554 E
Introduction
Data Sheet
20
Rev. 1.2, 2006-01-26
Local loop, payload loop and remote loop for diagnostic purposes. Automatic payload loop and remote loop
switching is possible with In-Band and Out-Band loop codes
Per channel power-down function
Low power device, either two power supply voltages 1.8 V and 3.3 V or a single supply of 3.3 V
Frame Aligner
Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704 (E1) and for 1544 kbit/s according to ITU-
T G.704 and JT G.704 (T1/J1)
Programmable frame formats:
E1: Doubleframe, CRC multiframe (E1)
T1: 4-frame multiframe (F4,FT), 12-frame multiframe (F12, D3/4), extended superframe (F24, ESF), remote
switch mode (F72, SLC96)
Selectable conditions for recover/loss of frame alignment
CRC4 to non-CRC4 interworking according to ITU-T G. 706 Annex B (E1)
Error checking via CRC4 procedures according to ITU-T G. 706 (E1)
Error checking via CRC6 procedures according to ITU-T G. 706 and JT G.706 (T1/J1)
Performs synchronization in ESF format according to NTT requirements (J1)
Alarm and performance monitoring per second 16-bit counter for CRC-errors, framing errors, code violations,
error monitoring via E-bit and SA6-bit (E1), errored blocks, PRBS bit errors
Insertion and extraction of alarm indication signals (AIS, remote/yellow alarm,…)
Remote alarm generation/checking according to ITU JT-G.704 in ESF-format (J1)
Remote defect indication according to ITU-T G.775
IDLE code insertion for selectable channels
Single-bit defect insertion
Flexible system clock frequency for receiver and transmitter
Supports programmable system data rates with independent receive/transmit shifts:
E1: 2.048, 4.096, 8.192 and 16.384 Mbit/s (according to H.100/H.110 bus)
T1/J1: 2.048, 4.096, 8.192, 16.384 Mbit/s and 1.544, 3.088, 6.176, 12.352 Mbit/s
with integrated multiplexer and de-multiplexer
Elastic store for receive and transmit clock wander and jitter compensation; controlled slip capability and slip
indication
Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass
Provides different time slot mapping modes
Supports fractional E1 or T1/J1 access
Flexible transparent modes
Programmable In-band loop code detection and generation (TR62411)
Programmable Out-band loop code (BOM) detection (ANST-T1 403))
Channel loop back, line loop back or payload loop back capabilities (TR54016)
Flexible pseudo-random binary sequence generator and monitor
Clear channel capabilities (T1/J1)
Loop-timed mode
Signaling Controller
Three HDLC controllers per channel, attachable either to the line or system side, including 128 byte FIFO
buffers, perform Bit stuffing, CRC check and generation, flag generation, flag and address recognition,
handling of bit oriented functions
Supports signaling system #7 delimitation, alignment and error detection according to ITU-Q.703 processing
of fill in signaling units, processing of errored signaling units
ANSI T1.404 bit-oriented messages (BOM) generates periodical performance reports
CAS/CAS-BR controller with last look capability, enhanced CAS-register or system interface access and
freeze signaling indication
DL-channel protocol for ESF format according to ANSI T1.403 specification or according to AT&T TR54016
(T1/J1)
Flexible DL-bit access for F72 (SLC96) format (T1/J1)
Generates periodical performance report according to ANSI T1. 403, accessible by microcontroller