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Data Sheet
131
Rev. 1.2, 2006-01-26
QuadFALC
TM
PEF 22554 E
Functional Description E1
Write 33
H into REGFP
Write 00
B‘ into REGFD
Write B3
B into REGFP
Note that these wander configuration is reset by a receive reset (REGFD_E.RRES = 1)
Using this programming and 2 Hz for the corner frequency of the DCO-R, the output wander is given by curve 2.
4.1.7
Framer/Synchronizer (E1)
The following functions are performed:
Synchronization on pulse frame and multiframe
Error indication when synchronization is lost. In this case, AIS is sent automatically to the system side and
remote alarm is sent to the remote end if enabled.
Initiating and controlling of re synchronization after reaching the asynchronous state. This can be done
automatically by the QuadFALC
TM or user controlled over the asynchronous, SPI or SCI interface.
Detection of remote alarm indication from the incoming data stream.
Separation of service bits and data link bits. This information is stored in status registers.
Generation of various maskable interrupt statuses of the receiver functions.
Generation of control signals to synchronize the CRC checker, and the receive elastic buffer.
If programmed and applicable to the selected multiframe format, CRC checking of the incoming data stream is
done by generating check bits for a CRC submultiframe according to the CRC4 procedure (refer to ITU-T G.704).
These bits are compared with those check bits that are received during the next CRC submultiframe. If there is at
least one mismatch, the CRC error counter (16 bit) is incremented.
4.1.8
Receive Elastic Buffer (E1)
The received bit stream is stored in the receive elastic buffer, see Figure 24. The size of the elastic buffer can be
configured independently for the receive and transmit direction. Programming of the receive buffer size is done by
SIC1.RBS(1:0):
RBS(1:0) = 00
B: two frame buffer or 512 bits. Maximum of wander amplitude (peak-to-peak): 190 UI (1
UI = 488 ns). Average delay after performing a slip: 1 frame or 256 bits
RBS(1:0) = 01
B: one frame buffer or 256 bits. Maximum of wander amplitude: 100 UI. Average delay after
performing a slip: 128 bits,
RBS(1:0) = 10
B: short buffer or 96 bits. Maximum of wander amplitude: 38 UI. Average delay after performing
a slip: 48 bits,
RBS(1:0) = 11
B: Bypass of the receive elastic buffer
The functions are:
Clock adoption between system clock (SCLKR) and internally generated route clock (recovered line clock), see
Compensation of input wander and jitter.
Frame alignment between system frame and receive route frame
Reporting and controlling of slips
Controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-parallel data
which is circularly written to the elastic buffer using internally generated receive route clock.
Writing of received data from the line is controlled by the internally generated route clock (recovered line clock).
Reading of stored data is controlled either by the system clock sourced by SCLKR or by the DCO-R of the receive
jitter attenuator and the synchronization pulse (SYPR) together with the programmed offset values for the receive
time slot/clock slot counters. After conversion into a serial data stream, the data is given out on port RDO. If the
receive buffer is bypassed programming of the time slot offset is disabled and data is clocked off with internally
generated route clock (recovered line clock) instead of SCLKR.
In one frame or short buffer mode the delay through the receive buffer is reduced to an average delay of 128 or
46 bits. In bypass mode the time slot assigner is disabled. In this case SYPR programmed as input is ignored.
Slips are performed in all buffer modes except the bypass mode. After a slip is detected the read pointer is
adjusted to one half of the current buffer size.