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QuadFALC
TM
PEF 22554 E
Signaling Controller Operating Modes
Data Sheet
688
Rev. 1.2, 2006-01-26
Cyclic Transmission (fully transparent)
If the extended transparent mode is selected, the QuadFALC
TM supports the continuous transmission of the
contents of the transmit FIFOs.
After having written 1 up to 64 bytes to XFIFO (XFIFO2, XFIFO3), the command XREP&XTF
(CMDR = 00100100
B =24H) forces the QuadFALC
TM to transmit the data stored in XFIFO to the remote end
repeatedly.
Note: The cyclic transmission continues until a reset command (CMDR.SRES) is issued or with resetting of
CMDR.XREP, after which continuous “1”s are transmitted. During cyclic transmission the XREP-bit has to
be set with every write operation to CMDR. The same handling applies to CMDR2 and CMDR3 for HDLC
channels 2 an 3.
12.3.2
CRC on/off Features
As an option in HDLC mode the internal handling of the received and transmitted CRC checksum can be
influenced via control bits CCR2.RCRC and CCR2.XCRC (channel 2: CCR3.RCRC2, CCR3.XCRC2, channel 3:
CCR4.RCRC3, CCR4.XCRC3).
Receive Direction
The received CRC checksum is always assumed to be in the 2 last bytes of a frame (CRC-ITU), immediately
preceding a closing flag. If CCR2.RCRC is set, the received CRC checksum is written to RFIFO where it precedes
the frame status byte (contents of register RSIS). The received CRC checksum is additionally checked for
correctness. If HDLC mode is selected, the limits for “Valid Frame” check are modified (refer to description of bit
RSIS.VFR).
Transmit Direction
If CCR2.XCRC is set, the CRC checksum is not generated internally. The checksum has to be provided via the
transmit FIFO (XFIFO) as the last two bytes. The transmitted frame is closed automatically by a closing flag only.
The QuadFALC
TM does not check whether the length of the frame, i.e. the number of bytes to be transmitted is
valid or not.
12.3.3
Receive Address Pushed to RFIFO
The address field of received frames can be pushed to the receive FIFOs (first one or two bytes of a frame). This
function is used together with extended address recognition. It is enabled by setting control bit CCR2.RADD
(CCR3.RADD2, CCR4.RADD3).
12.3.4
HDLC Data Transmission
In transmit direction 2 x 64 byte FIFO buffers are provided for each HDLC channel. After checking the XFIFO
status by polling bit SIS.XFW (SIS2.XFW2, SIS3,XFW3) or after an interrupt ISR1.XPR (ISR5.XPR2, ISR5.XPR3,
Transmit Pool Ready), up to 32 bytes can be entered by the external micro controller to the XFIFOs.
The transmission of a frame can be started by issuing a XTF or XHF command via the command registers. If the
transmit command does not include an end of message indication (CMDR.XME, CMDR3.XME2, CMDR4.XME3),
the QuadFALC
TM will repeatedly request for the next data block by means of an XPR interrupt as soon as no more
than 64bytes are stored in the XFIFO, i.e. a 32-byte pool is accessible to the external micro controller.
This process is repeated until the external micro controller indicates the end of message by XME command, after
which frame transmission is finished correctly by appending the CRC and closing flag sequence. Consecutive
frames can share a flag, or can be transmitted as back-to-back frames, if service of the XFIFOs is fast enough.
In case no more data is available in the XFIFOs prior to the arrival of XME, the transmission of the frame is
terminated with an abort sequence and the external micro controller is notified by interrupt ISR1.XDU (ISR4.XDU2,
ISR5.XDU3). The frame can be aborted by software using CMDR.SRES (CMDR3.SRES2, CMDR4.SRES3).
The data transmission sequence, from the external micro controller’s point of view, is outlined in Figure 131.