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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
293
Register 0x1A1: Per-PHY Counter Control
Bit
Type
Function
Default
31:18
R
Unused
X
17
R/W
RWB
1
16
R
BUSY
X
15
R/W
CLP0_CLRONRD
0
14
R/W
CLP1_CLRONRD
0
13
R/W
RM_CLRONRD
0
12
R/W
OAM_CLRONRD
0
11
R/W
INVOAMRM_CLRONRD
0
10
R/W
INVAL_CLRONRD
0
9
R/W
NZGFC_CLRONRD
0
8
R/W
TO_CLRONRD
0
7:6
R
Reserved
0
5:0
R/W
PHYID[5:0]
0
A write to this register initiates an access to the Per-PHY counting RAM. The RWB bit
determines if this access is a read or a write. While the transfer is pending, the BUSY bit will be
high. The BUSY bit will go low when the transfer into the holding registers is complete.
PHYID[5:0]
The PHYID field determines which PHYs counts get read or written. PHY ID’s greater than
47 will not result in any action and the holding registers will stay unchanged.
BUSY
When the BUSY bit is active it indicates that an access request to the PHY counts is pending.
While this bit is high the contents of the holding registers is undefined. After writing to this
register to initiate an access, the microprocessor should poll this register and wait for the
BUSY to go low before reading the counts from the holding register. An access to the PHY
counts is typically completed within 22 cycles.
CLP0_CLRONRD
If CLP0_CLRONRD is logic 1, then after a read of a set of PHY counts, a write is
automatically initiated to set the CLP0 count to 0. The writes are done in such a way that no
counts are missed. If CLRONRD = ‘0’, no write back to clear the count bits is initiated.