![](http://datasheet.mmic.net.cn/330000/PM7325_datasheet_16444376/PM7325_371.png)
S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
371
Register 0x2C5: Bypass SDQ Indirect Configuration
Bit
Type
Function
Default
31:16
Unused
X
15
R/W
FIFO_ENBL
0
14
R/W
FIFO_TYPE
0
13:7
R/W
FIFO_SIZE[6:0]
0000001
6:0
R/W
FIFO_PTR[6:0]
0000000
FIFO_PTR[6:0]
This 7-bit pointer specifies where a FIFO starts in the 3072-word SRAM space. It is specified
in blocks, where a block is defined as 32 words (128 bytes). The range of this pointer should
be 0 to 95; any other values will cause unpredictable effects. This pointer is calculated and
programmed based on the number of FIFOs required by the system and the size of each
FIFO. The rules governing this calculation are stated in section 13.1.
FIFO_SIZE[6:0]
This 7-bit number denotes the size of a FIFO in blocks. The size of a FIFO is related to the
bandwidth. Table 43 below shows the suggested FIFO size based on the PHY bandwidth.
Since there are altogether 96 blocks in the SRAM, the legal range for this number is 2 to 96;
settings outside this range are reserved and may cause unpredictable effects.
Table 43 Suggested FIFO Size Encoding
FIFO size
(blocks)
FIFO size
(bytes)
Bandwidth
1
128
Not Supported
2
256
STS-1 or less
6
768
STS-3
24
3072
STS-12 or STS-48
96
12288
STS-48
Note that packets occupy a number of bytes equal to their packet length rounded up to the
next multiple of 4 bytes. A FIFO size of 1 block is not supported.
FIFO_TYPE
This bit must be set to logic 1 for all FIFOs in the Bypass SDQ to indicate that packets are
being handled.