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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
335
HEC
The HEC bit is used to indicate whether the HEC/UDF word is included in ATM cells. When
the value is ‘1’, the ATM cells contain the HEC/UDF word. When the value is ‘0’, the ATM
cells do not contain the HEC/UDF word. In any event, the HEC is undefined at the ATM
layer, and will not be calculated by RxPhy. This bit cannot be changed during operation and
can only be changed when RXPRST is logic one.
SERVEOVRD
The SERVEOVRD bit is used to configure whether Servicing Override is performed in
UTOPIA. Normally, the switch or TM device is responsible for polling and servicing the
FIFOs of this interface. The servicing Override option allows this interface to appear as a
single PHY to the switch or TM, with the RxPhy block choosing which PHY queues to
service, using the Polling and Servicing Calendar. When the value is ‘1’, the servicing
override is engaged. When the value is ‘0’, the servicing override is not engaged and expects
normal MPHY polling and servicing from the switch or TM. This bit cannot be changed
during operation and can only be changed when RXPRST is logic one.
PRELEN[1:0]
The PRELEN bits are used to indicate the size of the prepend applied to the ATM cells to
external blocks. A value of ‘00’ indicates no prepend word. A value of ‘01’ indicates 1
prepend word. A value of ‘10’ indicates 2 prepend words A value of ‘11’ is invalid. These bits
cannot be changed during operation and can only be changed when RXPRST is logic one.
These bits apply to all PHY channels. The sum of PRELEN + POSTLEN must not exceed 2,
or correct operation is not guaranteed
.
POSTLEN[1:0]
The POSTLEN bits are used to indicate the size of the postpend applied to the ATM cells. A
value of ‘00’ indicates no postpend word. A value of ‘01’ indicates 1 postpend word. A value
of ‘10’ indicates 2 postpend words. A value of ‘11’ is invalid. These bits cannot be changed
during operation and can only be changed when RXPRST is logic one. These bits apply to all
PHY channels. The sum of PRELEN + POSTLEN must not exceed 2, or correct operation is
not guaranteed
.
RSXPAUSE[1:0]
RSXPAUSE bits control the number of clocks to pause between transfers as per POS-PHY
Level 3 specification. These bits are effective in POS mode only. The default setting is ‘00’
meaning no pause will occur between transfers resulting in maximum bandwidth usage. As
setting of ‘01’ indicates 1 clock between transfers and a setting of ‘10’ indicates 2 clocks
between transfers. A setting of ‘11’ is reserved. These bits cannot be changed during
operation and can only be changed when RXPRST is logic one.