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S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
412
14.2.2 Egress UL3 Interface
In the Egress direction, the S/UNI-ATLAS-3200 provides a Tx PHY interface on the input
(system) side, and a Tx Link interface on the output (PHY) side. Selection of ingress vs. egress
mode and POS vs UL3 signalling must be performed at startup.
Figure 42 shows the Egress TxLink interface that interfaces to the PHY side; the TxPhy interface
operates in the same way, but the signal names start with TPU, and the S/UNI-ATLAS-3200 plays
the role of the PHY.
Figure 42 Egress UTOPIA Logical Timing
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
......
P5
P3
P4
P5
P0
P1
P3
P4
P0
P1
P2
......
P4
P3
P5
P3
P0
P5
P4
......
H1
D10
D11
H1
D1
......
D11
.......
......
D1
D2
......
......
......
P4
D0
D0
......
P0
P1
......
P1
P2
TLU_CLK
TLU_ADDR[5:0]
TLU_CLAV
TLU_WRENB
TLU_SOC
TLU_DAT[31:0]
TLU_PAR
The S/UNI-ATLAS-3200 can send a cell to a PHY port only when the PHY port has indicated to
the ATM layer device that it is ready to receive at least one cell. The PHY device will indicate this
by asserting the Transmit Cell Available (TLU_CLAV). The PHY device must deassert the
TxClav 2 cycles after sampling TLU_SOC high if it cannot accept the immediate transfer of a
subsequent cell.
TxPhy UTOPIA Logical Timing
In the egress direction the S/UNI-ATLAS-3200 input cell/packet interface acts as a Transmit PHY
layer device, and the upstream device acts as an ATM Layer device, for the purposes of UTOPIA
Level 3 cell transfer.