
S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
362
Register 0x2A6: Output SDQ Cells and Packets Count
This register is used to read the count of the number of cells in the FIFO specified in the Output
SDQ Indirect Address register. The count reflects the write-side perspective, and will not react
immediately to reads. The counts are latched when the S/UNI-ATLAS-3200 Identity / Load
Counts Register is written to, or when any of the Output SDQ Count registers are written to.
While the transfer is in progress, the TIP bit is asserted in the Output SDQ Control Register and
S/UNI-ATLAS-3200 Identity / Load Counts Register, and remains high for the interval of the
update. TIP goes low once the counts are valid. Once TIP goes low, the count for the PHY
specified in the Output SDQ Address register will be placed in this register.
The recommended sequence for using this register is:
1.
Program the desired PHYID in the Output SDQ Indirect Address Register. Typically this
would be done while setting RWB = 1.
2.
Execute a write to this register
3.
Poll TIP in the Output SDQ Control Register until it becomes 0.
4.
Read the value in this register.
Bit
Type
Function
Default
31:12
Unused
X
11:0
R
COUNT[11:0]
0
COUNT[11:0]
This read-only field holds the last sampled count for the FIFO requested by PHYID[5:0] in
the FIFO indirect address register. Since each FIFO can hold up to 3072 POS packets or 192
ATM cells, this count does not saturate or roll over.