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參數(shù)資料
| 型號(hào)： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 104/112頁(yè) |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
-8
QSM
REFERENCE MANUAL
CPOL — Clock Polarity
1 = The inactive state value of SCK is high.
0 = The inactive state value of SCK is low.
CPHA — Clock Phase
1 = Data is changed on the leading edge of SCK and captured on the following
edge of SCK.
0 = Data is captured on the leading edge of SCK and changed on the following
edge of SCK.
SPBR — Serial Clock Baud Rate
The QSPI internally generates the baud rate for SCK, the frequency of which is pro-
grammable by the user. The following equation determines the SCK baud rate:
SCK Baud Rate = System Clock/(2 * SPBR)
or
SPBR = System Clock/(2 * SCK Baud Rate Desired)
where SPBR equals {2, 3, 4,..., 255}.
SPE — QSPI Enable
1 = The QSPI is enabled and the pins allocated by QSM register PQSPAR are con-
trolled by the QSPI.
0 = The QSPI is disabled and the seven QSPI pins can be used as general-purpose
I/O pins, regardless of the values in PQSPAR.
Bit 13
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 11
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 10
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bits per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
13
14
15
SPCR1
— QSPI Control Register 1
15
14
13
SPE
RESET:
0
0
0
$YFFC1A
1
12
11
10
9
8
7
6
5
4
3
2
0
DSCKL
DTL
0
0
1
0
0
0
0
0
0
0
1
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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