參數(shù)資料
型號(hào)： QSMRM
英文描述： QSMRM QSM Queued Serial Module Reference Manual
中文描述： QSMRM QSM排隊(duì)串行模塊參考手冊(cè)
文件頁(yè)數(shù)： 21/112頁(yè)
文件大?。?/td> 1496K
代理商： QSMRM
QSM
REFERENCE MANUAL
CONFIGURATION AND CONTROL
MOTOROLA
3-5
PORTQS and DDRQS (refer to
3.3.1 QSM Port Data Register (PORTQS)
and
3.3.3 QSM Data Direction Register (DDRQS)
The pin control registers should be initialized in the order PORTQS and then DDRQS,
thus establishing the default state and direction of the QSM pins.
For configuration of the QSPI submodule, initialize as follows:
RAM (refer to
4.3.6 QSPI RAM
)
PQSPAR (refer to
3.3.2 QSM Pin Assignment Register (PQSPAR)
Assignment of appropriate pins to the QSPI must be made with this register.
SPCR0 (refer to
4.3.1 QSPI Control Register 0 (SPCR0)
The system designer must choose a transfer rate (baud) for operation in master mode,
an appropriate clock phase, clock polarity, and the number of bits to be transferred in
a serial operation. Master/slave mode select (MSTR) must be set to configure the
QSPI for master mode or cleared to configure operation in slave mode. WOMQ should
be set to enable or cleared to disable wired-OR mode operation.
SPCR1 (refer to
4.3.2 QSPI Control Register 1 (SPCR1)
— SPE must be set to enable the QSPI; this register should be written last.
— DTL allows the user to program a delay after any serial transfer, which is in-
voked by the DT bit for any serial transfer.
— DSCKL allows the user to set a delay before SCK (after PCS valid), which is
invoked by the DSCK bit for any transfer.
SPCR2 (refer to
4.3.3 QSPI Control Register 2 (SPCR2)
— NEWQP and ENDQP, respectively, determine the beginning of a queue and
the number of serial transfers (up to 16) to be considered a complete queue.
— WREN is set to enable queue wraparound, and WRTO helps determine the
address used in wraparound mode.
— SPIFIE is set to enable interrupts when SPIF is asserted.
SPCR3 (refer to
4.3.4 QSPI Control Register 3 (SPCR3)
HALT may be used for program debug, and HMIE is set to enable CPU interrupts
when HALTA or MODF is asserted; LOOPQ is set only to enable a feedback loop that
can be used for self-test mode.
For configuration of the SCI submodule, initialize as follows:
SCCR0 (refer to
5.2.1 SCI Control Register 0 (SCCR0)
The system designer must choose a transfer rate (baud) for serial transfer operation.
SCCR1 (refer to
5.2.2 SCI Control Register 1 (SCCR1)
— The type of serial frame (8- or 9-bit) and the use of parity must be determined
by M, PE, and PT.
— For receive operation, the system designer must consider use and type of
wakeup (WAKE, RWU, ILT, ILIE). The receiver must be enabled (RE) and,
usually, RIE should be set.
— For transmit operation, the transmitter must be enabled (TE) and, usually, TIE
should be set. The use of wired-OR mode (WOMS) must also be decided.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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