
QSM
REFERENCE MANUAL
QSPI SUBMODULE
MOTOROLA
4-1
SECTION 4
QSPI SUBMODULE
The QSPI submodule communicates with external peripherals and other MCUs via
synchronous serial bus. The QSPI is fully compatible with the serial peripheral inter-
face (SPI) systems found on other Motorola devices such as the M68HC11 and
M68HC05 Families. It has all of the capabilities of the SPI system as well as several
new features. The following paragraphs describe the features, block diagram, pin de-
scriptions, programmer's model (memory map) inclusive of registers, and the master
and slave operation of the QSPI.
4.1 Features
Standard SPI features are listed below, followed by a list of the additional features of-
fered on the QSPI:
Full-Duplex, Three-Wire Synchronous Transfers
Half-Duplex, Two-Wire Synchronous Transfers
Master or Slave Operation
Programmable Master Bit Rates
Programmable Clock Polarity and Phase
End-of-Transmission Interrupt Flag
Master-Master Mode Fault Flag
Easily Interfaces to Simple Expansion Parts (A/D converters, EEPROMS, display
drivers, etc.)
QSPI-Enhanced features are as follows:
Programmable Queue — up to 16 preprogrammed transfers
Programmable Peripheral Chip-Selects — four pins select up to 16 SPI chips
Wraparound Transfer Mode — for autoscanning of serial A/D (or other) peripher-
als, with no CPU overhead
Programmable Transfer Length — from 8–16 bits inclusive
Programmable Transfer Delay — from 1 μs to 0.5 ms (at 16.78 MHz)
Programmable Queue Pointer
Continuous Transfer Mode — up to 256 bits
4.1.1 Programmable Queue
A programmable queue allows the QSPI to perform up to 16 serial transfers without
CPU intervention. Each transfer corresponds to a queue entry containing all the infor-
mation needed by the QSPI to independently complete one serial transfer. This unique
feature greatly reduces CPU/QSPI interaction, resulting in increased CPU and system
throughput.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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