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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 32/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
4-4
QSPI SUBMODULE
QSM
REFERENCE MANUAL
registers must be initialized in proper order before the QSPI is enabled to ensure de-
fined operation. Only the control registers must adhere to the order of sequence pre-
scribed in
3.1 Overall QSM Configuration Summary
. Write register SPCR1 last
when setting up the QSPI, as this register contains the QSPI enable bit (SPE). Assert-
ing this bit starts the QSPI. QSPI control registers are reset to a defined state and may
then be changed by the CPU. Reset values are shown below each register.
In general, rewriting the same value into a control register does not affect the QSPI
operation with the exception of NEWQP (bits [3:0]) in SPCR2. Rewriting the same val-
ue to these bits causes the RAM queue pointer to restart execution at the designated
location.
If control bits are to be changed, the CPU should halt the QSPI first. With the exception
of SPCR2, writing a different value into a control register while the QSPI is enabled
may disrupt operation. SPCR2 is buffered, preventing any disruption of the current se-
rial transfer. After completion of the current serial transfer, the new SPCR2 values be-
come effective.
4.3.1 QSPI Control Register 0 (SPCR0)
SPCR0 contains parameters for configuring the QSPI before it is enabled. Although
the CPU can read and write this register, the QSM has read-only access.
MSTR — Master/Slave Mode Select
1 = QSPI is system master and can initiate transmission to external SPI devices.
0 = QSPI is a slave device, and only responds to externally generated serial trans-
fers.
MSTR configures the QSPI for either master or slave mode operation. This bit is
cleared on reset and may only be written by the CPU, not the QSM.
Table 4-1 QSPI Registers
Address
$YFFC18, 9
$YFFC1A, B
$YFFC1C, D
$YFFC1E
$YFFC1F
$YFFD00–1F
$YFFD20–3F
$YFFD40–4F
Name
SPCR0
SPCR1
SPCR2
SPCR3
SPSR
RAM
RAM
RAM
Usage
QSPI Control Register 0
QSPI Control Register 1
QSPI Control Register 2
QSPI Control Register 3
QSPI Status Register
QSPI Receive Data (16 Words)
QSPI Transmit Data (16 Words)
QSPI Command Control (8 Words)
SPCR0
— QSPI Control Register 0
$YFFC18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSTR
WOMQ
BITS
CPOL CPHA
SPBR
RESET:
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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