
QSM
REFERENCE MANUAL
INDEX
MOTOROLA
I-3
Receive 0-7/Transmit 0-7 (R0-R7/T0-T7) 5-13
Receive 8/Transmit 8 (R8/T8) 5-12
Receive Data (RXD) 2-1, 5-16
Receive Data RAM 4-13
Receive Data Register (RDR) 5-10, 5-11, 5-12, 5-16,
5-20
Receive Data Register Full Flag (RDRF) 5-10, 5-17, 5-20,
5-21, B-5
Receiver Active Flag (RAF) 5-11, B-5
Receiver Bit Processor 5-16, 5-17
Receiver Enable (RE) 3-5, 5-2, 5-9, 5-16, 5-20, B-4
Receiver Functional Operation 5-20
Receiver Interrupt Enable (RIE) 5-8, B-4
Receiver Operation 5-15
Receiver Wakeup (RWU) 3-5, 5-6, 5-9, 5-22, B-4
RIE 5-8, B-4
RT1-RT16 5-16
RWU 3-5, 5-6, 5-9, 5-22, B-4
RXD 2-1, 5-16
RXD pin 5-16, 5-20, 5-21
–S–
SBK 5-9, 5-15, B-5
SCBR 5-5, 5-16
SCI 1-1
SCCR0 3-5, 5-2, 5-5
SCCR1 2-1, 3-5, 5-2, 5-6, 5-13, 5-15, 5-16, 5-20,
5-22
SCDR 3-6, 5-9, 5-10, 5-12, 5-20
SCI Baud 5-5
SCI Baud Clock Synchronization Signal (SYNC) 3-8
SCI Baud Rates 5-5
SCI Pins 2-1
SCI SUBMODULE 3-10
SCSR 3-6, 5-2, 5-6, 5-9, 5-10, 5-14
SCI Control Register 0 (SCCR0) 3-5, 5-2, 5-5
SCI Control Register 1 (SCCR1) 2-1, 3-5, 5-2, 5-6, 5-13,
5-15, 5-16, 5-20, 5-22
SCI Data Register (SCDR) 3-6, 5-9, 5-10, 5-12, 5-20
SCI Programmer's Model and Registers 5-2
SCI Receiver Block Diagram 5-3
SCI Status Register (SCSR) 3-6, 5-2, 5-6, 5-9, 5-10, 5-14
SCI SUBMODULE 5-1
SCI Transmitter Block Diagram 5-4
SCK 2-1, 2-2, 3-5, 3-10, 3-11, 4-5, 4-24, 4-26, 4-27, B-7
SCK Baud Rate 4-6
Send Break (SBK) 5-9, 5-15, B-5
Serial Clock (SCK) 2-1, 2-2, 3-5, 3-10, 3-11, 4-5, 4-24,
4-26, 4-27, B-7
Serial Clock Baud Rate (SPBR) 4-6, B-8
Serial Interface 1-1
SIGNAL DESCRIPTIONS 2-1
Slave Mode 1-1, 4-26
Slave Operation 4-26
Slave Select (SS) 4-12, 4-17
Slave Wraparound Mode 4-28
SPBR 4-6, B-8
SPCR0 2-1, 3-5, 4-4, 4-16
SPCR1 3-5, 4-4, 4-6, 4-24
SPCR2 3-5, 4-4, 4-8, 4-10, 4-11, 4-14, 4-16, 4-25, 4-28
SPCR3 3-5, 4-10
SPE 3-5, 4-4, 4-7, 4-12, 4-25, 4-26, 4-27, 4-28, B-8
SPI 4-1
SPI Bus Master 4-17
SPI Master Arbitration 4-24
SPIFIE 3-5, 4-8, 4-11, 4-25, 4-28, B-9
TSBD 3-8, B-2
SPI Finished Interrupt Enable (SPIFIE) 3-5, 4-8, 4-11,
4-25, 4-28, B-9
SPI Test Scan Path Select (TSBD) 3-8, B-2
SPIF 3-5, 4-9, 4-11, 4-27, 4-28, B-10
SPSR 4-11, 4-12, 4-13, 4-16, 4-25, 4-28
SS 4-12, 4-17
Start Bit 5-13
Start bit 5-16
Start Search Example 1 5-17
Start Search Example 2 5-17
Start Search Example 3 5-18
Start Search Example 4 5-18
Start Search Example 5 5-19
Start Search Example 6 5-19
Start Search Example 7 5-20
STOP 3-4, 3-6
Stop Bit 5-13
Stop Enable (STOP) 3-4, 3-6
Supervisor/Unrestricted (SUPV) 1-3, 3-4, 3-7
SUPV 1-3, 3-4, 3-7
SYNC 3-8
–T–
TC 5-9, 5-10, B-5
TCIE 5-8, B-4
TDR 5-10, 5-12, 5-13, 5-14
TDRE 5-9, 5-10, 5-14, 5-15, B-5
TE 2-1, 3-5, 5-2, 5-8, 5-13, 5-15, B-4
Test Memory Map (TMM) 3-8
TIE 3-5, 5-8, B-4
TMM 3-8
TQSM 3-8, B-2
Transfer Delay 4-2
Transfer Length 4-2
Transfer Mode 4-2
Transmit Complete Flag 5-10
Transmit Complete Flag (TC) 5-9, 5-10, B-5
Transmit Complete Interrupt Enable (TCIE) 5-8, B-4
Transmit Data (TXD) 2-1, 3-10, 3-11, 4-5, 5-13, 5-14,
5-15, B-7
Transmit Data RAM 4-13, 4-14
Transmit Data Register (TDR) 5-10, 5-12, 5-13, 5-14
Transmit Data Register Empty Flag (TDRE) 5-9, 5-10,
5-14, 5-15, B-5
Transmit Interrupt Enable (TIE) 3-5, 5-8, B-4
Transmitter Enable (TE) 2-1, 3-5, 5-2, 5-8, 5-13, 5-15, B-4
Transmitter Operation 5-13
TXD 2-1, 3-10, 3-11, 4-5, 5-13, 5-14, 5-15, B-7
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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