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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 81/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
USING THE QSPI FOR ANALOG DATA AQUISITION
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
A-3
able data/clock phase relationship. The baud rate and the delay between transfers are
also programmable. The QSPI has a maximum transfer speed of one-fourth the
MC68332 system clock speed.
Since the QSPI is capable of operation as a master or as a slave, all pins are bidirec-
tional.
Figure A-2
shows a typical master mode configuration. The slave peripherals
are selected via the peripheral chip-select pins, PCS[0:3], and the serial clock is pro-
vided by the SCK pin. QSPI output data is presented on the master out slave in (MOSI)
pin, and input is taken from the master in slave out (MISO) pin.
Figure A-2 Master Mode Representation of the QSPI
One of the most powerful elements of the QSPI is its queue.
Figure A-3
depicts the
structure of the QSPI queue RAM. The queue may contain up to 16 entries, each con-
sisting of a transmit word, a receive word, and a command control byte. The transmit
and receive words are from 8 to 16 bits long and are LSB justified. For any given queue
entry, the transmit and receive words are the same length.
Figure A-3 Organization of the QSPI Ram
An important subset of the queue RAM is the command control RAM.
Figure A-4
PERIPHERAL
CHIP-SELECTS
PCS3
PCS2
PCS1
PCS0/
SS
SCK
MOSI
SERIAL
CLOCK
QSPI DATA
QSPI
SUBMODULE
RECEIVE
DATA
TRANSMIT
DATA
D00
D1E
D20
D3E
WORD
D40
D4F
COMMAND
CONTROL
BYTE
WORD
0
F
ENTRY
F
Freescale Semiconductor, Inc.
n
.
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