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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 22/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
3-6
CONFIGURATION AND CONTROL
QSM
REFERENCE MANUAL
Once the transmitter is configured, data is not sent until TDRE and TC are
cleared. To clear TDRE and TC, the SCSR read must be followed by a write to
SCDR (either the lower byte or the entire word).
3.2 QSM Global Registers
The QSM global registers contain system parameters used by both the QSPI and the
SCI submodules. These registers define parameters used by the QSM to interface
with the CPU and other system modules. The four global registers are listed in
Table
3-3
.
3.2.1 QSM Configuration Register (QSMCR)
QSMCR contains parameters for interfacing to the CPU and the intermodule bus
(IMB). This register can be modified only when the CPU is in supervisor mode.
STOP — Stop Enable
1 = QSM clock operation stopped
0 = Normal QSM clock operation
STOP places the QSM into a low power state by disabling the system clock in most
parts of the module. QSMCR is the only register guaranteed to be readable while
STOP is asserted. The QSPI RAM is not readable; however, writes to RAM or any reg-
ister are guaranteed valid while STOP is asserted. STOP may be negated by the CPU
and by reset.
The system software must stop each submodule before asserting STOP to avoid com-
plications at restart and to avoid data corruption. The SCI submodule receiver and
transmitter should be disabled, and the operation should be verified for completion be-
fore asserting STOP. The QSPI submodule should be stopped by asserting the HALT
bit in SPCR3 and by asserting STOP after the HALTA flag is set.
FRZ1 — Freeze1
1 = Halt the QSM (on a transfer boundary)
0 = Ignore the FREEZE signal on the IMB
FRZ1 determines what action is taken by the QSM when the FREEZE signal of the
IMB is asserted. FREEZE is asserted whenever the CPU enters the background
mode.
Table 3-3 QSM Global Registers
Address
$YFFC00
$YFFC02
$YFFC04
$YFFC05
Name
QSMCR
QTEST
QILR
QIVR
Usage
QSM Configuration Register
QSM Test Register
QSM Interrupt Level Register
QSM Interrupt Vector Register
QSMCR
— QSM Configuration Register
$YFFC00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
FRZ1
FRZ0
0
0
0
0
0
SUPV
0
0
0
IARB
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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