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| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 20/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
3-4
CONFIGURATION AND CONTROL
QSM
REFERENCE MANUAL
3.1 Overall QSM Configuration Summary
After reset, the QSM remains in an idle state, requiring initialization of several registers
before any serial operations may begin execution. The following registers, fields, and
bits are fully described later in this section. A general sequence guide for initialization
follows:
QSMCR (refer to
3.2.1 QSM Configuration Register (QSMCR)
This register must be initialized to properly configure:
Interrupt arbitration identification number used by the entire QSM module
Supervisor/unrestricted bit (SUPV)
FREEZE and/or STOP configuration; which should remain cleared to zero for nor-
mal operation.
QIVR and QILR (refer to
3.2.3 QSM Interrupt Level Register (QILR)
and
3.2.4
QSM Interrupt Vector Register (QIVR)
These registers are written to choose the base vector number for the entire QSM mod-
ule and individual interrupt levels for the QSPI and SCI submodules.
RAF
RDRF
RE
RWU
SBK
SCK
SPE
SPIF
SPIFIE
STOP
SUPV
SYNC
T[8:0]
TC
TCIE
TDRE
TE
TIE
TMM
TQSM
TSBD
TXD
WAKE
WOMQ
WOMS
WREN
WRTO
Receiver Active Flag
Receive Data Register Full Flag
Receiver Enable
Receiver Interrupt Enable
Receiver Wakeup
Send Break
Serial Clock
QSPI Enable
QSPI Finished Flag
SPI Finished Interrupt Enable
Stop
Supervisor/Unrestricted
SCI Baud Clock Sync Signal
Transmit 8–0
Transmit Complete Flag
Transmit Complete Interrupt Enable
Transmit Data Register Empty Flag
Transmit Enable
Transmit Interrupt Enable
Test Memory Map
Test QSM Enable
SPI Test Scan Path Select
Transmit Data
Wakeup Type
Wired-OR Mode for QSPI Pins
Wired-OR Mode for SCI Pins
Wrap Enable
Wrap To Select
SCSR
SCSR
SCCR1
SCCR1
SCCR1
SCCR1
SCI
SCI
SCI
SCI
SCI
SCI
QSM
QSPI
QSPI
QSPI
QSM
QSM
QSM
SCI
SCI
SCI
SCI
SCI
SCI
QSM
QSM
QSM
QSM
SCI
QSPI
SCI
QSPI
QSPI
DDRQS/PORTQS
SPCR1
SPSR
SPCR2
QSMCR
QSMCR
QTEST
SCDR
SCSR
SCCR1
SCSR
SCCR1
SCCR1
QTEST
QTEST
QTEST
DDRQS/PORTQS
SCCR1
SPCR0
SCCR1
SPCR2
SPCR2
Table 3-2 Bit/Field Quick Reference Guide (Sheet 2 of 2)
Bit/Field Mnemonic
Function
Register
Register Location
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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