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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 68/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
5-12
SCI SUBMODULE
QSM
REFERENCE MANUAL
FE — Framing Error Flag
1 = Framing error or break occurred on the received data
0 = No framing error on the received data
FE is set when the SCI receiver detects a zero where a stop bit (one) was to occur. A
framing error results when the frame boundaries in the received bit stream are not syn-
chronized with the receiver bit counter. FE is not set until the entire frame is received
and RDRF is set. Although an interrupt is not explicitly associated with FE, an interrupt
may be generated with RDRF and FE checked in this manner. A break can also cause
FE to be set. FE is cleared when SCSR is read with FE set, followed by a read of reg-
ister RDR.
PF — Parity Error Flag
1 = Parity error occurred on the received data
0 = No parity error occurred on the received data
PF is set when the SCI receiver detects a parity error. PF is not set until the entire
frame is received and RDRF is set. Although an interrupt is not explicitly associated
with PF, an interrupt may be generated with RDRF and PF checked in this manner. PF
is cleared when SCSR is read with PF set, followed by a read of the register RDR.
5.2.4 SCI Data Register (SCDR)
SCDR contains two data registers, both at the same address. The first register is the
RDR, which is a read-only register. It contains data received over the SCI serial inter-
face. Initially, data is received into the receive serial shifter and is transferred by the
receiver into RDR. The second register is the SCI TDR, which is a write-only register.
Data to be transmitted over the SCI serial interface is written to TDR. The transmitter
transfers this data to the transmit serial shifter, adding on additional format bits before
the data is sent out on the SCI serial interface.
R8/T8 — Receive 8/Transmit 8
This bit is the ninth serial data bit received (R8) when the SCI system is configured for
a 9-bit data operation (M = 1). When the SCI system is configured for an 8-bit data op-
eration (M = 0), this bit has no meaning or effect.
This bit is the ninth serial data bit transmitted (T8) when the SCI system is configured
for 9-bit data operation (M = 1). When the SCI system is configured for an 8-bit data
operation (M = 0), this bit has no meaning or effect.
Accesses to the lower byte of SCDR triggers the mechanism for clearing the status
bits or for initiating transmissions whether byte, word, or long-word accesses are used.
SCDR
— SCI Data Register
$YFFC0E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
RESET:
0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
U
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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