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參數(shù)資料
| 型號(hào)： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊(duì)串行模塊參考手冊(cè) |
| 文件頁(yè)數(shù)： | 106/112頁(yè) |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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MOTOROLA
-10
QSM
REFERENCE MANUAL
Bits [15:11] — Not Implemented
LOOPQ — QSPI Loop Mode
1 = Feedback path enabled
0 = Feedback path disabled
HMIE — HALTA and MODF Interrupt Enable
1 = HALTA and MODF interrupts enabled
0 = HALTA and MODF interrupts disabled
HALT — Halt
1 = Halt enabled
0 = Halt not enabled
This bit is used by the CPU to stop the QSPI on a queue boundary.
* SPCR3 — QSPI Control Register 3
SPIF — QSPI Finished Flag
1 = QSPI finished
0 = QSPI not finished
SPIF is set when the QSPI finishes executing the last command determined by the ad-
dress contained in ENDQP in SPCR2.
MODF — Mode Fault Flag
1 = Another SPI node requested to become the network SPI master while the QSPI
was enabled in master mode (MSTR = 1), or the PCS0/SS pin was incorrectly
pulled low by external hardware.
0 = Normal operation
HALTA — Halt Acknowledge Flag
1 = QSPI halted
0 = QSPI not halted
HALTA is asserted by the QSPI when it has come to an orderly halt at the request of
the CPU, through the assertion of HALT.
Bit 4 — Not Implemented
CPTQP — Completed Queue Pointer
CPTQP contains the queue pointer value of the last command in the queue that was
completed.
SPSR
— QSPI Status Register
15
$YFFC1F
1
CPTQP
8
7
6
5
4
0
3
2
0
SPCR3*
SPIF
MODF
HALTA
RESET:
0
0
0
0
0
0
0
0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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