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| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 25/112頁 |
| 文件大小： | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
CONFIGURATION AND CONTROL
MOTOROLA
3-9
After initialization, QIVR determines which two vectors in the exception vector table
are to be used for QSM interrupts. The QSPI and SCI submodules have separate in-
terrupt vectors adjacent to each other. Both submodules use the same interrupt vector
with the least significant bit (LSB) determined by the submodule causing the interrupt.
The value of INTV0 used during an IACK cycle is supplied by the bus interface unit
(BIU). During an IACK, INTV[7:1] are driven on the DATA[7:1] lines. The INTV0 drives
line DATA0 with a zero for an SCI interrupt and with a one for a QSPI interrupt. Writes
to INTV0 have no meaning or effect. Reads of INTV0 return a value of one.
INTV0 is set to a logic level one when the QSPI generates an interrupt and set to a
logic level zero when the SCI generates an interrupt.
* QILR — QSM Interrupt Level Register
3.3 QSM Pin Control Registers
Table 3-3
identifies the three pin control registers of the QSM. The QSM determines
the use of nine pins, eight of which form a parallel port on the MCU. Although these
pins are used by the serial subsystems, any pin may alternately be assigned as gen-
eral-purpose I/O on a pin by pin basis. For use of these pins as general-purpose I/O,
they must not be assigned to the QSPI submodule in register PQSPAR. To avoid brief-
ly driving incorrect data, the first byte to be output should be written before register
DDRQS is configured for any output pins. DDRQS should then be written to determine
the direction of data flow on the pins and to output the value contained in register
PORTQS for all pins defined as outputs. Subsequent data for output is then written to
PORTQS.
3.3.1 QSM Port Data Register (PORTQS)
PORTQS determines the actual input or output value of a QSM port pin if the pin is
defined in PQSPAR as general-purpose I/O. All QSM port pins may be used as gen-
eral-purpose I/O. Writes to this register affect the pins defined as outputs; reads of this
register return the actual value of the pins.
QIVR
— QSM Interrupt Vector Register
$YFFC05
15
8
7
6
5
4
3
2
1
0
QILR*
INTV[7:0]
RESET:
0
0
0
0
1
1
1
1
Table 3-4 QSM Pin Control Registers
Address
$YFFC15
$YFFC16
$YFFC17
Name
PORTQS
PQSPAR
DDRQS
Usage
QSM Port Data Register
QSM Pin Assignment Register
QSM Data Direction Register
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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