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參數(shù)資料
| 型號： | QSMRM |
| 英文描述： | QSMRM QSM Queued Serial Module Reference Manual |
| 中文描述： | QSMRM QSM排隊串行模塊參考手冊 |
| 文件頁數(shù)： | 33/112頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | QSMRM |
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QSM
REFERENCE MANUAL
QSPI SUBMODULE
MOTOROLA
4-5
WOMQ — Wired-OR Mode for QSPI Pins
1 = All QSPI port pins designated as output by DDRQS function as open drain out-
puts and can be wire-ORed to other external lines.
0 = Output pins have normal outputs instead of open-drain outputs.
WOMQ allows the QSPI pins to be wire-ORed, regardless of whether they are used
as general-purpose outputs or as QSPI outputs. WOMQ affects the QSPI pins whether
the QSPI is enabled or disabled. This bit does not affect the SCI submodule transmit
(TXD) pin, which has its own WOMS bit in an SCI control register.
BITS — Bits Per Transfer
In master mode, BITS determines the number of data bits transferred for each serial
transfer in the queue that has the command control bit (BITSE of the QSPI RAM) equal
to one. If BITSE equals zero for a command, 8 bits are transferred for that command
regardless of the value in BITS. Data transfers from 8 to 16 bits are supported. Illegal
(reserved) values all default to 8 bits. BITSE is not used in slave mode. All transfers
are of the length specified by BITS.
Table 4-2
shows the number of bits per transfer.
CPOL — Clock Polarity
1 = The inactive state value of SCK is high.
0 = The inactive state value of SCK is low.
CPOL is used to determine the inactive state value of the serial clock (SCK). CPOL is
used in conjunction with CPHA to produce the desired clock-data relationship between
master and slave device(s). QSPI clock/data timing relationships are specified in indi-
vidual microcontroller user's manuals.
CPHA — Clock Phase
1 = Data is changed on the leading edge of SCK and captured on the following
edge of SCK.
0 = Data is captured on the leading edge of SCK and changed on the following
edge of SCK.
Table 4-2 Bits per Transfer if Command Control Bit BITSE = 1
Bits [13:10]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits per Transfer
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
9
10
11
12
13
14
15
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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