參數(shù)資料
型號: SAA6750
廠商: NXP Semiconductors N.V.
英文描述: Encoder for MPEG2 image recording EMPIRE
中文描述: 為MPEG2編碼器帝國的形象記錄
文件頁數(shù): 12/60頁
文件大?。?/td> 217K
代理商: SAA6750
2000 May 03
12
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
Notes
1.
All input pins, input/output pins (in input mode), output pins (in 3-state mode) and open-drain output pins are 5.0 V
tolerant.
This pin is recommended to be set to ground or to the supply voltage V
DD
via a resistor.
In accordance with the “IEEE 1149.1”standard.
Special function of pin TRST:
a) For board designs without boundary scan implementation, pin TRST must be connected to ground.
b) Pin TRST provides easy initialization of the internal BST circuit. By applying a LOW it can be used to force the
internal Test Access Port (TAP) controller to the Test-Logic-Reset state (normal operating) at once.
2.
3.
4.
DATA14
DATA15
V
DD
DATA16
DATA17
DATA18
DATA19
V
SS
DATA20
DATA21
DATA22
DATA23
V
DD
DATA24
DATA25
DATA26
DATA27
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
input/output
input/output
supply
input/output
input/output
input/output
input/output
ground
input/output
input/output
input/output
input/output
supply
input/output
input/output
input/output
input/output
3
3
3
3
3
3
3
3
3
3
3
3
3
3
DRAM data interface bit 14
DRAM data interface bit 15
supply voltage for pad ring
DRAM data interface bit 16
DRAM data interface bit 17
DRAM data interface bit 18
DRAM data interface bit 19
ground for pad ring
DRAM data interface bit 20
DRAM data interface bit 21
DRAM data interface bit 22
DRAM data interface bit 23
supply voltage for pad ring
DRAM data interface bit 24
DRAM data interface bit 25
DRAM data interface bit 26
DRAM data interface bit 27
SYMBOL
PIN
INPUT/OUTPUT
(1)
I
max
(mA)
DESCRIPTION
The 208 pins are divided in following groups:
Video input port (11 pins):
8 data pins and 3 control pins.
Data output port (23 pins):
16 data pins and 7 control pins.
GPIO port (15 pins):
12 data pins and 3 control pins.
DRAM (77 pins):
64 data pins
9 address pins
4 control pins.
Others (14 pins):
1 video clock input pin
3 pins related to the I
2
C-bus
1 pin for reset control
7 pins for test purposes
1 pin not connected
1 pin for internal test purposes.
Supply (68 pins):
16 core supply pins
18 I/O cell supply pins
16 core ground pins
18 I/O cell ground pins.
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