參數(shù)資料
型號: SAA6750
廠商: NXP Semiconductors N.V.
英文描述: Encoder for MPEG2 image recording EMPIRE
中文描述: 為MPEG2編碼器帝國的形象記錄
文件頁數(shù): 48/60頁
文件大?。?/td> 217K
代理商: SAA6750
2000 May 03
48
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
Notes
1.
2.
All input pins are 5 V tolerant.
In accordance with the “IEEE1149.1”standard the input pins TCK, TDI, TMS and TRST must have an internal pull-up
resistor.
The outputs, which can be switched in the 3-state mode, are 5 V tolerant due to the bus application of 5 V.
The open-drain outputs, which can be switched off, are 5 V tolerant due to the 5 V application.
3.
4.
5.
6.
7.
1
2
T
cy
applies for first column address after a row address, T
cy
for all other modes.
Typical values are maximum when data is available.
I/O pins of the I
2
C-bus interface must not obstruct the SDA and SCL lines if the supply voltage V
DD
is switched off.
Data output interface timing: DTACK_RDY, I_MN, CSN, AS_ALE, DS_RDN and AD15 to AD0;
see Figs 16 and 17 and Table 13
t
as
t
ah
t
az
t
cs
t
dhr
t
dsr
t
idl
t
drtL
t
drtH
t
rwi
t
dz
address set-up time
address hold time
address 3-state time
CSN set-up time
data hold time read
data set-up time read
AS pulse width
DTACK reaction time LOW
DTACK reaction time HIGH
read/write or data strobe pulse width
data 3-state
15
20
20
0
0
0
60
60
0
2T
cy
T
cy
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
note 6
I
2
C-bus interface: SCL and SDA;
note 7
f
SCL
V
IL
V
IH
I
I
V
OL
SCL clock frequency
LOW-level input voltage
HIGH-level input voltage
input current
LOW-level output voltage
100
0.7V
DD
10
0
0
1.3
0.6
100
0.6
0.6
400
0.3V
DD
5.5
+10
0.4
0.6
0.3
0.3
kHz
V
V
μ
A
V
V
μ
s
μ
s
μ
s
μ
s
ns
μ
s
μ
s
3 mA sink current
6 mA sink current
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;STA
t
SU;STO
SCL LOW time
SCL HIGH time
rise time SDA and SCL
fall time SDA and SCL
data set-up time
hold time START condition
set-up time STOP condition
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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