參數(shù)資料
型號: SAA6750
廠商: NXP Semiconductors N.V.
英文描述: Encoder for MPEG2 image recording EMPIRE
中文描述: 為MPEG2編碼器帝國的形象記錄
文件頁數(shù): 33/60頁
文件大小: 217K
代理商: SAA6750
2000 May 03
33
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.9.4
I
2
C-
BUS MEMORIES AND REGISTERS
Eight different SRAM memories and registers may be written or read via the I
2
C-bus. Each has a specific subaddress.
This chapter will explain the purpose of these storages and how they have to be used.
7.9.4.1
Allocation of subaddresses
Following table shows which memories or registers are allocated to the subaddresses 00H to 07H:
Table 19
Subaddresses and related memories
SUBADDRESS
(HEX)
STORAGE
NAME
DESIGN
BLOCK
DEPTH
(WORDS)
WIDTH(BITS)
DESCRIPTION
00
quantizatio
n matrix
SRAM
microcode
SRAM
microcode
ROM table
microcode
constants
serial
output
register
serial input
register
MBP
128
8
SRAM memory containing a constant table
for the macroblock processor quantization
function
SRAM memory containing the microcode of
the ASIP
SRAM memory containing the microcode
ROM table of the ASIP
SRAM memory containing the microcode
constants of the ASIP
register bank that can be written by the ASIP;
contents depending on the ASIP software
01
ASIP
1024
177
02
ASIP
512
24
03
ASIP
256
24
04
ASIP
7
24
05
ASIP
14
24
register bank that can be read by the ASIP;
used to control the ASIP externally; the
function of the register settings is depending
on the ASIP software
register containing the hardware control bits
of the SAA6750H
06
control
register
internal use none
I
2
C-bus
1
160
07
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