參數(shù)資料
型號: SAA6750
廠商: NXP Semiconductors N.V.
英文描述: Encoder for MPEG2 image recording EMPIRE
中文描述: 為MPEG2編碼器帝國的形象記錄
文件頁數(shù): 29/60頁
文件大?。?/td> 217K
代理商: SAA6750
2000 May 03
29
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.6.3.2
Interface definition
The data output interface uses in total 23 pins. Pins AD0 to AD15 carry data and address information. 7 pins are
reserved for control purposes. Partly, the functionality of these pins changes with the selected address or protocol mode
(see Tables 13 and 14).
Table 13
List of pins data output port
Table 14
Protocol mode depending pins
PIN NAME
PIN TYPE
DESCRIPTION
AD0 to AD15
input/output
internal address decoding: multiplexed address/data bus; external address decoding:
non-multiplexed data bus
protocol mode depending functionality; see Table 14
internal address decoding: not used; connect to HIGH; external address decoding:
data output port select input
protocol mode depending functionality; see Table 14
protocol mode depending functionality; see Table 14
select protocol mode: LOW is Motorola-style protocol mode (must be set to logic 0);
HIGH is reserved mode
LOW indicates that the fullness of the output buffer is below the programmable lower
watermark value; see Table 22
LOW indicates that the fullness of the output buffer is higher than the programmable
higher watermark value; see Table 22
AS_ALE
CSN
input
input
DS_RDN
DTACK_RDY
I_MN
input
output
input
LRQN
output
URQN
output
PIN NAME
MOTOROLA-STYLE PROTOCOL MODE
RESERVED MODE
AS_ALE
DS_RDN
DTACK_RDY
AS
DS
DTACK
address strobe
data strobe
data transfer acknowledge
ALE
RDN
RDY
reserved
reserved
reserved
7.6.3.3
Status reporting data output buffer
The data output port of the SAA6750H provides
information about the status of the internal 4 Mbit output
buffer. Two signals that are available via
pins LRQN and URQN are related to internal buffer
watermarks. The external host may use this information to
control the data stream in a way that highest rates are
possible without out-of-data or buffer-overflow situations.
The watermark levels are programmable via the I
2
C-bus
(see Table 22).
The lower watermark reporting may be used by the host to
prevent out-of-data situations. The fullness of the data
output buffer is monitored. If the current value is below the
thresholdprogrammedincontrolword‘BS_BUFFERlower
level’ in the I
2
C-bus control register, the signal LRQN goes
to LOW. The host may use this information to stop
requesting data. Value ‘BS_BUFFER lower level’ has a
range of 0 to 63. If the value is set to 0, LRQN will not be
activated. The threshold can be selected in 64-bit steps.
The upper watermark reporting may be used by the host to
prevent data overflow of the output buffer of the
SAA6750H. The fullness of the data output buffer located
in the external DRAM is monitored. If the current value is
two times or more than two times the value programmed in
bytes ‘BS_BUFFER upper level’ in the I
2
C-bus control
register, the signal URQN goes to LOW. The host may use
this information to start requesting data. If it does not, an
internal buffer overflow may result in loss of data.
Value ‘BS_BUFFER upper level’ has a valid range of
1 to 32752. The threshold can be selected in 128-bit
steps. The maximum watermark value equals 4 Mbit.
During reset mode, ‘BS_BUFFER lower level’ and
‘BS_BUFFER upper level’ are set to logic 0. The I
2
C-bus
control register values BS_BUFFER should be initialized
with the desired values before starting operating mode.
If ‘BS_ BUFFER lower level’ has a value greater than 0,
LRQN will be LOW as long as no valid data is available.
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