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參數(shù)資料
| 型號(hào)： | SAA6750 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Encoder for MPEG2 image recording EMPIRE |
| 中文描述： | 為MPEG2編碼器帝國(guó)的形象記錄 |
| 文件頁(yè)數(shù)： | 13/60頁(yè) |
| 文件大?。?/td> | 217K |
| 代理商： | SAA6750 |
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2000 May 03
13
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
Fig.2 Pin configuration.
handbook, halfpage
SAA6750H
1
2
1
5
1
52
156
105
MBK768
7
FUNCTIONAL DESCRIPTION
7.1
Global architecture description
7.1.1
G
ENERAL
The SAA6750H has a multi-processor architecture.
The different processing and control modules are not
locked to each other but run independently within the limits
of the global scheduling. The data transfer between the
processing units is carried out via FIFO memories or the
external DRAM (see Fig.1).
The set of functions of the SAA6750H is determined to
a high extent by the microcode of the internal Application
Specific Instruction-set Processor (ASIP). Detailed
information is given in the software specification.
Global settings and selection of the operating modes are
carried out via the I
2
C-bus (see Sections 7.2 and 7.9).
7.1.2
A
RCHITECTURE STRUCTURE
The architecture consist of a data processing, a control
and a memory part.
7.1.2.1
Data processing part
The data processing flow can be split-up as follows:
Line based processing:
Video front-end and formatter (see Section 7.3) including:
1.
4 : 2 : 2 to 4 : 2 : 0 pre-filter
2.
Optional SIF subsampling.
The video front-end processes the incoming video data
and writes it to the external DRAM.
Macroblock based processing:
MacroBlock Processor (MBP) (see Section 7.4) including:
1.
Discrete Cosine Transformation/Inverse Discrete
Cosine Transformation (DCT/IDCT)
2.
Variable Length Encoding/Run Length Encoding
(VLE/RLE)
3.
Motion Estimation/Motion Compensation (ME/MC)
4.
Motion Compensation Noise Reduction (MCNR)
5.
Quantization/Inverse Quantization (Q/IQ)
6.
Frame/Field (FF) reshuffling and ZigZag (ZZ) scan.
The MBP gets the pre-processed video data from the
external DRAM and performs the data compression.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6750H | Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA7102 | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:12; Connector Shell Size:28; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| SAA7102E | Digital video encoder |
| SAA7102H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6750H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA6752HS/V103 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA6752HS/V103,557 | 功能描述:IC AUD/VID ENCODER MPEG 208-SQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| SAA6752HS/V104 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
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