參數(shù)資料
型號(hào)： SAA6750
廠商： NXP Semiconductors N.V.
英文描述： Encoder for MPEG2 image recording EMPIRE
中文描述： 為MPEG2編碼器帝國(guó)的形象記錄
文件頁(yè)數(shù)： 14/60頁(yè)
文件大?。?/td> 217K
代理商： SAA6750
2000 May 03
14
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
Bitstream based processing:
Bitstream assembly (see Section 7.5) (Pre-packer,
Packer, Stuffing unit and output buffer) and Data output
port (see Section 7.6).
The bitstream processing part gets the compressed data
from the MBP and the header information from the control
part. It provides an MPEG2 compliant Elementary
Stream (ES) at the output.
7.1.2.2
Control part
The control part consists of three modules:
1.
Application Specific Instruction-set Processor (ASIP)
(see Section 7.7):controlstheMBP,generatesmotion
vectors, headers and stuffing information
2.
The global controller (see Section 7.8): generates the
global scheduling information for the MBP, the DRAM
interface and the ASIP
3.
The I
2
C-bus interface and controller (see Section 7.9):
download of ASIP microcode, tables and constants as
well as MBP quantizer table, used for external control
settings, allows communication between ASIP and
application environment.
7.1.2.3
Memory part
The control and data processing modules exchange data
via internal FIFOs and the external DRAM:
1.
DRAM interface (see Section 7.10); provides access
to the external DRAM memory
2.
FIFO memories (see Section 7.11); a number of
FIFOs of different size is used to connect internal
processing units.
7.2
Start-up and operating modes
7.2.1
S
TART
-
UP REQUIREMENTS
Simultaneously with power-on, the SAA6750H requires
a LOW level at pin RESETN. This external reset has to be
kept active until the external video clock signal VCLK has
been running stable within the specified limits for at least
10 clock cycles (see Chapter “Quick reference data”).
A suitable combination of RESETN and clock signal is e.g.
provided by Philips product family SAA7111A. For proper
reset behaviour and operation pin TRST has to be LOW.
After power-on and the related internal reset the
initialization via the I
2
C-bus has to be carried out
(see Section 7.9.5). It should be noted that a delay of at
least 0.5 ms between the end of RESETN LOW state and
start of the I
2
C-bus initialization sequence is required.
See Table 1 for information about the operating modes.
7.2.2
R
ESET PROCESSING
The SAA6750H has internally an asynchronous and
a synchronous reset processing.
The asynchronous reset is directly derived from the
external reset signal RESETN and gets active as soon as
RESETN becomes LOW. It is not depending on the
external clock signal. The asynchronous reset forces the
SAA6750H into reset mode which does directly affect the
behaviour of the output and I/O pins (see Table 2).
This does guarantee a defined state of the pins even if no
clock signal is available. In addition it initiates the internal
synchronous reset which gets active as soon as the VCLK
signal is available.
The internal synchronous reset is controlled by RESETN
and the settings of control bits E_ST and E_SP.
For properoperatingtheexternalclocksignalVCLKhasto
be stable within the specified limits.
The internal synchronous reset gets active if RESETN is
LOW or by setting the control bits E_ST and E_SP to soft
reset mode (see Table 1). It does affect all internal
modules except the I
2
C-bus controller and therefore also
the output and I/O pins (see Table 2). In addition, but only
if combined with an external reset RESETN, it does reset
the I
2
C-bus control register. It does not affect the contents
of the embedded microcode and constant memories
(see Section 7.9.4).
See Table 2 for detailed information about the impact of
external and internal reset signals as well as control bit
settings on the behaviour of internal modules and output
pins.
After release of the external reset or setting back
bits E_ST and E_SP to operating mode, the internal
synchronous reset remains active for 7562 clock cycles
(approximately 260
μ
s). During this time the DRAM
initialization sequence is carried out
(see Section 7.10.3.2). All other internal modules except
theI
2
C-buscontrolregister stayinreset modeforthistime.
The external DRAM will not be refreshed during internal
synchronous reset.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA6750H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE
SAA6752HS 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SAA6752HS/V103 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
SAA6752HS/V103,557 功能描述:IC AUD/VID ENCODER MPEG 208-SQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類(lèi)型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱(chēng):Q4645799
SAA6752HS/V104 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
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