參數(shù)資料
型號: SAA6750
廠商: NXP Semiconductors N.V.
英文描述: Encoder for MPEG2 image recording EMPIRE
中文描述: 為MPEG2編碼器帝國的形象記錄
文件頁數(shù): 36/60頁
文件大小: 217K
代理商: SAA6750
2000 May 03
36
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.9.4.8
Serial input register
Register bank that can be read by the ASIP. Used to control the ASIP externally. The function of register settings is
depending on the ASIP software. A description will be part of the software specification.
The valid address range reaches from 01H to 0EH. Any data sent by the I
2
C-bus to address 00H will always be
overwritten by an internal signal.
7.9.4.9
Control register
Register bank used to control internal signals. The allocation of control bits in the register is shown in Table 21.
The function of the specific bits is described in Table 22.
During external reset, all register bits will be set to logic 0.
During initialization all 20 bytes starting with the MSB and ending with the LSB (control) have to be sent by the I
2
C-bus
in one go.
SUBADDRESS
(HEX)
STORAGE NAME
DESIGN BLOCK
DEPTH
(WORDS)
WIDTH
(BITS)
DATA TRANSFER MODE
05
serial input register
ASIP
14
24
random access write mode
SUBADDRESS
(HEX)
STORAGE NAME
DESIGN BLOCK
DEPTH
(WORDS)
WIDTH
(BITS)
DATA TRANSFER MODE
06
control register
I
2
C
1
160
write mode
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