參數(shù)資料
型號: SAA6750
廠商: NXP Semiconductors N.V.
英文描述: Encoder for MPEG2 image recording EMPIRE
中文描述: 為MPEG2編碼器帝國的形象記錄
文件頁數(shù): 17/60頁
文件大?。?/td> 217K
代理商: SAA6750
2000 May 03
17
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.3.3
F
UNCTIONAL DESCRIPTION
7.3.3.1
General
The video front-end and formatter module consists of four
submodules:
1.
The 8-bit data interface and the related control signals
connect the SAA6750H to external data sources such
as e.g. Philips SAA711x product family
2.
The formatter submodule covers two main functions:
the processing of the synchronization information
(sync processing) and the processing of the picture
contents (line based processing)
3.
The luminance and chrominance submodules
generatetheaddressesintheexternalDRAMmemory
where the output data of the video front-end and
formatter module is stored.
The video front-end and formatter module offers various
operating modes. The appropriate setting can be selected
in the I
2
C-bus control register (see Tables 3 and 22).
It should be noted that changes of video standard or
synchronization settings are only allowed in init mode or
soft reset mode. See Section 7.2.3 for information of the
operating modes.
Table 3
Video front-end and formatter mode selection
Note
1.
X = don’t care.
CONTROL BITS
(1)
MODE
FUNCTION
STD
SS
SMOD
0
1
0
0
0
1
X
X
X
NTSC
PAL
NTSC-SIF
NTSC input signal processing (60 Hz and 720 pixels by 480 lines)
PAL input signal processing (50 Hz and 720 pixels by 576 lines)
NTSC input signal processing (60 Hz and 720 pixels by 480 lines);
SIF down-scaling active
PAL input signal processing (50 Hz and 720 pixels by 576 lines);
SIF down-scaling active
ITU-T 656 mode sync processing mode; sync information is
embedded in the video data input stream
external sync processing mode; sync information is provided via
pins FID, HSYNC and VSYNC
1
1
X
PAL-SIF
X
X
0
ITU-T 656
X
X
1
external sync
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