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參數(shù)資料
| 型號： | SAA6750 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Encoder for MPEG2 image recording EMPIRE |
| 中文描述： | 為MPEG2編碼器帝國的形象記錄 |
| 文件頁數(shù)： | 42/60頁 |
| 文件大?。?/td> | 217K |
| 代理商： | SAA6750 |
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2000 May 03
42
Philips Semiconductors
Product specification
Encoder for MPEG2 image recording
(EMPIRE)
SAA6750H
7.10.3.3
DRAM refresh
The DRAM interface takes care of periodically refresh of
the external DRAM. Refresh is carried out by addressing
the specific DRAM page. It should be noted that refresh
only works if the SAA6750H is in operating mode
(see Table 1).
7.10.3.4
Memory sharing
The SAA6750H can be part of a system in which it shares
the memory with other devices. To this end the DRAM
interface output ports of the SAA6750H can be put to
3-state respectively input state by an appropriate setting of
the I
2
C-bus control register (see Table 1). Another IC
cannot use the memory concurrently with the SAA6750H.
7.10.3.5
Scheduling
The DRAM interface allows access to the external DRAM
once every two clock cycles. Therefore the nominal ‘Fast
Page Mode Cycle Time’ is t
PC
= 74 ns for a 27 MHz clock.
If the DRAM address changes from one page to another
page, which means a change in the most significant 9 bits
of the address, a page transition occurs. A page transition
also happens, if the data direction changes from read to
write or vice versa (a change of the WEN signal).
A detailed description of the timing can be found in
Figs 13 and 14 and Chapter “Characteristics”.
All internal clients of the DRAM interface are served using
a round robin scheme where the access time of each client
can be programmed via the I
2
C-bus within some limits.
These settings are depending on the embedded
microcode and will be provided in the software package.
Within one macroblock-period, which is defined as
650 clock cycles of the 27 MHz system clock, all clients
have to be served at least with two accesses but the sum
of all client accesses is not allowed to exceed the time of
one macroblock period.
7.11
FIFO memories
The FIFOs are data buffers which connect the internal
processes. This kind of coupling is necessary because
due to the multi-processor architecture e.g. one process
may give bursts of data, while the next process consumes
the data at constant rate. The state of the FIFOs therefore
also has an impact on the process behaviour. As long as
the FIFO buffers are not full or empty, the depending
processes work at their normal speed. If a data read or
write request from or to a FIFO cannot be served, the
depending process is interrupted.
7.12
Clock distribution
The SAA6750H needs a video clock signal VCLK as
specified in Chapter “Quick reference data”. The external
clock signal has to be synchronous to the video input data
stream. In the standard application e.g. the clock signal is
provided by a SAA7111A colour decoder.
The internal clock generation unit creates all internal
processing clocks.
7.13
Input/output levels
All input and I/O pad cells are 5 V tolerant. The output and
I/O pad cells provide 3.3 V output levels.
See Chapters “Quick reference data” and “Limiting
values” for detailed information.
7.14
Boundary scan test
7.14.1
G
ENERAL
The SAA6750H has built-in logic and 5 dedicated pins to
support boundary scan testing, which allows board testing
without special hardware (nails). The SAA6750H follows
the “IEEE Std. 1149.1 - Standard Test Access Port and
Boundary Scan Architecture”set by the Joint Test Action
Group (JTAG) chaired by Philips.
The 5 special pins are Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).
The Boundary Scan Test (BST) functions BYPASS,
EXTEST, SAMPLE, CLAMP and IDCODE are all
supported (see Table 25). Details about the
JTAG BST-TEST can be found in the specification
“IEEE Std.1149.1”AfilecontainingthedetailedBoundary
Scan Description Language (BSDL) description of the
SAA6750H is available on request.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6750H | Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA7102 | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:12; Connector Shell Size:28; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| SAA7102E | Digital video encoder |
| SAA7102H | Digital video encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6750H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA6752HS/V103 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA6752HS/V103,557 | 功能描述:IC AUD/VID ENCODER MPEG 208-SQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| SAA6752HS/V104 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
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